int board_fit_config_name_match(const char *name)
{
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later()) {
if (!strcmp(name, "dra72-evm-revc"))
return 0;
} else if (!strcmp(name, "dra72-evm")) {
return 0;
}
} else if (!is_dra72x() && !strcmp(name, "dra7-evm")) {
return 0;
}
return -1;
}
void do_board_detect(void)
{
char *bname = NULL;
int rc;
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
if (board_is_dra74x_evm()) {
bname = "DRA74x EVM";
} else if (board_is_dra72x_evm()) {
bname = "DRA72x EVM";
} else {
/* If EEPROM is not populated */
if (is_dra72x())
bname = "DRA72x EVM";
else
bname = "DRA74x EVM";
}
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
"Board: %s REV %s\n", bname, board_ti_get_rev());
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char *name = "unknown";
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later())
name = "dra72x-revc";
else if (board_is_dra71x_evm())
name = "dra71x";
else
name = "dra72x";
} else {
name = "dra7xx";
}
set_board_info_env(name);
/*
* Default FIT boot on HS devices. Non FIT images are not allowed
* on HS devices.
*/
if (get_device_type() == HS_DEVICE)
env_set("boot_fit", "1");
omap_die_id_serial();
omap_set_fastboot_vars();
#endif
return 0;
}
void hw_data_init(void)
{
*prcm = &dra7xx_prcm;
if (is_dra72x())
*dplls_data = &dra72x_dplls;
else if (is_dra76x())
*dplls_data = &dra76x_dplls;
else
*dplls_data = &dra7xx_dplls;
*ctrl = &dra7xx_ctrl;
}
void recalibrate_iodelay(void)
{
if (is_dra72x()) {
__recalibrate_iodelay(core_padconf_array_essential,
ARRAY_SIZE(core_padconf_array_essential),
iodelay_cfg_array,
ARRAY_SIZE(iodelay_cfg_array));
} else {
__recalibrate_iodelay(dra74x_core_padconf_array,
ARRAY_SIZE(dra74x_core_padconf_array),
dra742_iodelay_cfg_array,
ARRAY_SIZE(dra742_iodelay_cfg_array));
}
}
void vcores_init(void)
{
if (board_is_dra74x_evm()) {
*omap_vcores = &dra752_volts;
} else if (board_is_dra72x_evm()) {
*omap_vcores = &dra722_volts;
} else {
/* If EEPROM is not populated */
if (is_dra72x())
*omap_vcores = &dra722_volts;
else
*omap_vcores = &dra752_volts;
}
}
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
return;
/* Do not enable VTT for DRA722 */
if (is_dra72x())
return;
/*
* EVM Rev G and later use gpio7_11 for DDR3 termination.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
if (!is_dra7xx()) {
writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
}
/* omap5432 does not use lpddr2 */
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif1_sdram_config_ext);
if (!is_dra72x())
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif2_sdram_config_ext);
if (is_omap54xx()) {
/* Disable DLL select */
io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
(*ctrl)->control_port_emif1_sdram_config);
io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
(*ctrl)->control_port_emif2_sdram_config);
} else {
writel(ioregs->ctrl_ddr_ctrl_ext_0,
(*ctrl)->control_ddr_control_ext_0);
}
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char *name = "unknown";
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later())
name = "dra72x-revc";
else if (board_is_dra71x_evm())
name = "dra71x";
else
name = "dra72x";
} else if (is_dra76x_abz()) {
name = "dra76x_abz";
} else if (is_dra76x_acd()) {
name = "dra76x_acd";
} else {
name = "dra7xx";
}
set_board_info_env(name);
/*
* Default FIT boot on HS devices. Non FIT images are not allowed
* on HS devices.
*/
if (get_device_type() == HS_DEVICE)
env_set("boot_fit", "1");
omap_die_id_serial();
omap_set_fastboot_vars();
/*
* Hook the LDO1 regulator to EN pin. This applies only to LP8733
* Rest all regulators are hooked to EN Pin at reset.
*/
if (board_is_dra71x_evm())
palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
#endif
#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
if (device_okay("/ocp/omap_dwc3_1@48880000"))
enable_usb_clocks(0);
if (device_okay("/ocp/omap_dwc3_2@488c0000"))
enable_usb_clocks(1);
#endif
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char *name = "unknown";
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later())
name = "dra72x-revc";
else
name = "dra72x";
} else {
name = "dra7xx";
}
set_board_info_env(name);
omap_die_id_serial();
#endif
return 0;
}
static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
{
const char **clk_names;
u32 *clk_rates;
int ret;
if (!is_dra72x() && !is_dra7xx())
return;
/* fixup DSP clocks */
clk_names = dra7_opp_dsp_clk_names;
clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
if (ret) {
printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
fdt_strerror(ret));
return;
}
/* fixup IVA clocks */
clk_names = dra7_opp_iva_clk_names;
clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
if (ret) {
printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
fdt_strerror(ret));
return;
}
/* fixup GPU clocks */
clk_names = dra7_opp_gpu_clk_names;
clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
if (ret) {
printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
fdt_strerror(ret));
return;
}
}
