static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size, uint32_t page_oob_size) { int ecc_strength; int max_ecc_strength_supported; /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */ if (is_mx6sx() || is_mx7()) max_ecc_strength_supported = 62; else max_ecc_strength_supported = 40; /* * Determine the ECC layout with the formula: * ECC bits per chunk = (total page spare data bits) / * (bits per ECC level) / (chunks per page) * where: * total page spare data bits = * (page oob size - meta data size) * (bits per byte) */ ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8) / (galois_field * mxs_nand_ecc_chunk_cnt(page_data_size)); return min(round_down(ecc_strength, 2), max_ecc_strength_supported); }
void init_aips(void) { struct aipstz_regs *aips1, *aips2, *aips3; aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ writel(0x77777777, &aips1->mprot0); writel(0x77777777, &aips1->mprot1); writel(0x77777777, &aips2->mprot0); writel(0x77777777, &aips2->mprot1); /* * Set all OPACRx to be non-bufferable, not require * supervisor privilege level for access,allow for * write access and untrusted master access. */ writel(0x00000000, &aips1->opacr0); writel(0x00000000, &aips1->opacr1); writel(0x00000000, &aips1->opacr2); writel(0x00000000, &aips1->opacr3); writel(0x00000000, &aips1->opacr4); writel(0x00000000, &aips2->opacr0); writel(0x00000000, &aips2->opacr1); writel(0x00000000, &aips2->opacr2); writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); if (is_mx6sx() || is_mx7()) { /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. */ writel(0x77777777, &aips3->mprot0); writel(0x77777777, &aips3->mprot1); /* * Set all OPACRx to be non-bufferable, not require * supervisor privilege level for access,allow for * write access and untrusted master access. */ writel(0x00000000, &aips3->opacr0); writel(0x00000000, &aips3->opacr1); writel(0x00000000, &aips3->opacr2); writel(0x00000000, &aips3->opacr3); writel(0x00000000, &aips3->opacr4); } }
static inline int gpt_has_clk_source_osc(void) { #if defined(CONFIG_MX6) if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul()) return 1; return 0; #else return 0; #endif }
void imx_set_wdog_powerdown(bool enable) { struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR; #ifdef CONFIG_MX7D struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR; #endif /* Write to the PDE (Power Down Enable) bit */ writew(enable, &wdog1->wmcr); writew(enable, &wdog2->wmcr); if (is_mx6sx() || is_mx6ul() || is_mx7()) writew(enable, &wdog3->wmcr); #ifdef CONFIG_MX7D writew(enable, &wdog4->wmcr); #endif }
/* i2c_num can be from 0 - 3 */ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) { u32 reg; u32 mask; u32 *addr; if (i2c_num > 3) return -EINVAL; if (i2c_num < 3) { mask = MXC_CCM_CCGR_CG_MASK << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1)); reg = __raw_readl(&imx_ccm->CCGR2); if (enable) reg |= mask; else reg &= ~mask; __raw_writel(reg, &imx_ccm->CCGR2); } else { if (is_mx6sll()) return -EINVAL; if (is_mx6sx() || is_mx6ul() || is_mx6ull()) { mask = MXC_CCM_CCGR6_I2C4_MASK; addr = &imx_ccm->CCGR6; } else { mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK; addr = &imx_ccm->CCGR1; } reg = __raw_readl(addr); if (enable) reg |= mask; else reg &= ~mask; __raw_writel(reg, addr); } return 0; }