int __init loki_sdhci_init(void)
{
int nominal_core_mv;
int min_vcore_override_mv;
int boot_vcore_mv;
u32 speedo;
struct board_info bi;
tegra_get_board_info(&bi);
if (bi.board_id == BOARD_E2548 && bi.sku == 0x0 && bi.fab == 0x0) {
tegra_sdhci_platform_data3.uhs_mask |= MMC_MASK_HS200;
tegra_sdhci_platform_data3.max_clk_limit = 102000000;
}
nominal_core_mv =
tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail);
if (nominal_core_mv) {
tegra_sdhci_platform_data0.nominal_vcore_mv = nominal_core_mv;
tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv;
tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv;
}
min_vcore_override_mv =
tegra_dvfs_rail_get_override_floor(tegra_core_rail);
if (min_vcore_override_mv) {
tegra_sdhci_platform_data0.min_vcore_override_mv =
min_vcore_override_mv;
tegra_sdhci_platform_data2.min_vcore_override_mv =
min_vcore_override_mv;
tegra_sdhci_platform_data3.min_vcore_override_mv =
min_vcore_override_mv;
}
boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail);
if (boot_vcore_mv) {
tegra_sdhci_platform_data0.boot_vcore_mv = boot_vcore_mv;
tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv;
tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv;
}
tegra_sdhci_platform_data0.max_clk_limit = 204000000;
speedo = tegra_fuse_readl(FUSE_SOC_SPEEDO_0);
tegra_sdhci_platform_data0.cpu_speedo = speedo;
tegra_sdhci_platform_data2.cpu_speedo = speedo;
tegra_sdhci_platform_data3.cpu_speedo = speedo;
platform_device_register(&tegra_sdhci_device3);
if (!is_uart_over_sd_enabled())
platform_device_register(&tegra_sdhci_device2);
platform_device_register(&tegra_sdhci_device0);
loki_wifi_init();
return 0;
}
int __init ardbeg_pinmux_init(void)
{
if (is_uart_over_sd_enabled()) {
tegra_pinmux_config_table(ardbeg_sdmmc3_uart_pinmux,
ARRAY_SIZE(ardbeg_sdmmc3_uart_pinmux));
/* On ST8, UART-A is the physical device for
* UART over uSD card
*/
set_sd_uart_port_id(0);
}
return 0;
}
int __init loki_pinmux_init(void)
{
struct board_info bi;
tegra_get_board_info(&bi);
if (bi.board_id == BOARD_P2530) {
loki_gpio_init_configure();
tegra_pinmux_config_table(loki_ffd_pinmux_common,
ARRAY_SIZE(loki_ffd_pinmux_common));
};
if (is_uart_over_sd_enabled()) {
tegra_pinmux_config_table(loki_sdmmc3_uart_pinmux,
ARRAY_SIZE(loki_sdmmc3_uart_pinmux));
/* On loki, UART-A is the physical device for
* UART over uSD card
*/
set_sd_uart_port_id(0);
}
return 0;
}
int __init ardbeg_sdhci_init(void)
{
int nominal_core_mv;
int min_vcore_override_mv;
int boot_vcore_mv;
u32 speedo;
struct board_info board_info;
nominal_core_mv =
tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail);
if (nominal_core_mv) {
tegra_sdhci_platform_data0.nominal_vcore_mv = nominal_core_mv;
tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv;
tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv;
}
min_vcore_override_mv =
tegra_dvfs_rail_get_override_floor(tegra_core_rail);
if (min_vcore_override_mv) {
tegra_sdhci_platform_data0.min_vcore_override_mv =
min_vcore_override_mv;
tegra_sdhci_platform_data2.min_vcore_override_mv =
min_vcore_override_mv;
tegra_sdhci_platform_data3.min_vcore_override_mv =
min_vcore_override_mv;
}
boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail);
if (boot_vcore_mv) {
tegra_sdhci_platform_data0.boot_vcore_mv = boot_vcore_mv;
tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv;
tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv;
}
if (of_machine_is_compatible("nvidia,laguna") ||
of_machine_is_compatible("nvidia,jetson-tk1"))
tegra_sdhci_platform_data2.wp_gpio = ARDBEG_SD_WP;
tegra_get_board_info(&board_info);
if (board_info.board_id == BOARD_E1780)
tegra_sdhci_platform_data2.max_clk_limit = 204000000;
/* E1780 and E1784 are using interposer E1816, Due to this the
* SDIO trace length got increased. So hard coding the drive
* strength to type A for these boards to support 204 Mhz */
if ((board_info.board_id == BOARD_E1780) ||
(board_info.board_id == BOARD_E1784)) {
tegra_sdhci_platform_data0.default_drv_type =
MMC_SET_DRIVER_TYPE_A;
}
tegra_sdhci_platform_data0.max_clk_limit = 204000000;
if (board_info.board_id == BOARD_E1781)
tegra_sdhci_platform_data3.uhs_mask = MMC_MASK_HS200;
if (board_info.board_id == BOARD_PM374 ||
board_info.board_id == BOARD_PM358 ||
board_info.board_id == BOARD_PM363 ||
board_info.board_id == BOARD_PM359)
tegra_sdhci_platform_data0.disable_clock_gate = 1;
/*
* FIXME: Set max clk limit to 200MHz for SDMMC3 for PM375.
* Requesting 208MHz results in getting 204MHz from PLL_P
* and CRC errors are seen with same.
*/
if (board_info.board_id == BOARD_PM375)
tegra_sdhci_platform_data2.max_clk_limit = 200000000;
speedo = tegra_fuse_readl(FUSE_SOC_SPEEDO_0);
tegra_sdhci_platform_data0.cpu_speedo = speedo;
tegra_sdhci_platform_data2.cpu_speedo = speedo;
tegra_sdhci_platform_data3.cpu_speedo = speedo;
if (board_info.board_id == BOARD_E1991 ||
board_info.board_id == BOARD_E1971) {
tegra_sdhci_platform_data0.uhs_mask =
MMC_UHS_MASK_SDR50 | MMC_UHS_MASK_DDR50;
tegra_sdhci_platform_data2.uhs_mask =
MMC_UHS_MASK_SDR50;
}
if (board_info.board_id == BOARD_PM374 ||
board_info.board_id == BOARD_PM359) {
tegra_sdhci_platform_data2.uhs_mask =
MMC_UHS_MASK_SDR50;
tegra_sdhci_platform_data0.uhs_mask =
MMC_UHS_MASK_SDR50;
tegra_sdhci_platform_data3.max_clk_limit = 200000000;
tegra_sdhci_platform_data2.max_clk_limit = 204000000;
}
platform_device_register(&tegra_sdhci_device3);
if (!is_uart_over_sd_enabled())
platform_device_register(&tegra_sdhci_device2);
/* No wifi module for PM375 */
if (board_info.board_id != BOARD_PM359 &&
board_info.board_id != BOARD_PM375) {
platform_device_register(&tegra_sdhci_device0);
ardbeg_wifi_init();
}
return 0;
}
