static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
{
u32 length;
struct axidma_priv *priv = dev_get_priv(dev);
u32 temp;
/* Wait for an incoming packet */
if (!isrxready(priv))
return -1;
debug("axiemac: RX data ready\n");
/* Disable IRQ for a moment till packet is handled */
temp = readl(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
writel(temp, &priv->dmarx->control);
if (!priv->eth_hasnobuf)
length = rx_bd.app4 & 0xFFFF; /* max length mask */
else
length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
#ifdef DEBUG
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
#endif
*packetp = rxframe;
return length;
}
static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
{
u32 length;
struct axidma_priv *priv = dev_get_priv(dev);
u32 temp;
/* Wait for an incoming packet */
if (!isrxready(priv))
return -1;
debug("axiemac: RX data ready\n");
/* Disable IRQ for a moment till packet is handled */
temp = in_be32(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
out_be32(&priv->dmarx->control, temp);
length = rx_bd.app4 & 0xFFFF; /* max length mask */
#ifdef DEBUG
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
#endif
*packetp = rxframe;
return length;
}
static int axiemac_recv(struct eth_device *dev)
{
u32 length;
struct axidma_priv *priv = dev->priv;
u32 temp;
/* Wait for an incoming packet */
if (!isrxready(dev))
return 0;
debug("axiemac: RX data ready\n");
/* Disable IRQ for a moment till packet is handled */
temp = in_be32(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
out_be32(&priv->dmarx->control, temp);
length = rx_bd.app4 & 0xFFFF; /* max length mask */
#ifdef DEBUG
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
#endif
/* Pass the received frame up for processing */
if (length)
NetReceive(rxframe, length);
#ifdef DEBUG
/* It is useful to clear buffer to be sure that it is consistent */
memset(rxframe, 0, sizeof(rxframe));
#endif
/* Setup RxBD */
/* Clear the whole buffer and setup it again - all flags are cleared */
memset(&rx_bd, 0, sizeof(rx_bd));
rx_bd.next = (u32)&rx_bd;
rx_bd.phys = (u32)&rxframe;
rx_bd.cntrl = sizeof(rxframe);
/* Write bd to HW */
flush_cache((u32)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache will contain previous packet */
flush_cache((u32)&rxframe, sizeof(rxframe));
/* Rx BD is ready - start again */
out_be32(&priv->dmarx->tail, (u32)&rx_bd);
debug("axiemac: RX completed, framelength = %d\n", length);
return length;
}
