int target_design(ivl_design_t des)
{
const char*path = ivl_design_flag(des, "-o");
if (path == 0) {
return -1;
}
out = fopen(path, "w");
if (out == 0) {
perror(path);
return -2;
}
fprintf(out, "module %s;\n", ivl_scope_name(ivl_design_root(des)));
/* Declare all the signals. */
draw_scoped_objects(des);
/* Declare logic gates. */
draw_scope_logic(ivl_design_root(des), 0);
/* Write out processes. */
ivl_design_process(des, show_process, 0);
fprintf(out, "endmodule\n");
fclose(out);
return 0;
}
/*
* This is the main entry point that ivl uses to invoke me, the code
* generator.
*/
int target_design(ivl_design_t des)
{
ivl_scope_t root = ivl_design_root(des);
const char*path = ivl_design_flag(des, "-o");
xnf = fopen(path, "w");
if (xnf == 0) {
perror(path);
return -1;
}
part = ivl_design_flag(des, "part");
if (part && (part[0] == 0))
part = 0;
arch = ivl_design_flag(des, "arch");
if (arch && (arch[0] == 0))
arch = 0;
if (arch == 0)
arch = "lpm";
device = device_from_arch(arch);
if (device == 0) {
fprintf(stderr, "Unknown architecture arch=%s\n", arch);
return -1;
}
/* Call the device driver to generate the netlist header. */
device->show_header(des);
/* Catch any behavioral code that is left, and write warnings
that it is not supported. */
ivl_design_process(des, show_process, 0);
/* Get the pads from the design, and draw them to connect to
the associated signals. */
show_pads(root);
/* Scan the scopes, looking for gates to draw into the output
netlist. */
show_scope_gates(root, 0);
show_constants(des);
/* Call the device driver to close out the file. */
device->show_footer(des);
fclose(xnf);
xnf = 0;
return 0;
}
int target_design(ivl_design_t des)
{
ivl_scope_t*root_scopes;
unsigned nroot = 0;
unsigned idx;
const char*path = ivl_design_flag(des, "-o");
if (path == 0) {
return -1;
}
out = fopen(path, "w");
if (out == 0) {
perror(path);
return -2;
}
for (idx = 0 ; idx < ivl_design_disciplines(des) ; idx += 1) {
ivl_discipline_t dis = ivl_design_discipline(des,idx);
fprintf(out, "discipline %s\n", ivl_discipline_name(dis));
}
ivl_design_roots(des, &root_scopes, &nroot);
for (idx = 0 ; idx < nroot ; idx += 1) {
fprintf(out, "root module = %s;\n",
ivl_scope_name(root_scopes[idx]));
show_scope(root_scopes[idx], 0);
}
while (udp_define_list) {
struct udp_define_cell*cur = udp_define_list;
udp_define_list = cur->next;
show_primitive(cur->udp, cur->ref);
free(cur);
}
ivl_design_process(des, show_process, 0);
fclose(out);
return stub_errors;
}