/*
* Draw a single logic gate. Escape the name so that it is preserved
* completely. This drawing is happening in the root scope so signal
* references can remain hierarchical.
*/
static int draw_logic(ivl_net_logic_t net)
{
unsigned npins, idx;
const char*name = ivl_logic_name(net);
switch (ivl_logic_type(net)) {
case IVL_LO_AND:
fprintf(out, " and \\%s (", name);
break;
case IVL_LO_BUF:
fprintf(out, " buf \\%s (", name);
break;
case IVL_LO_OR:
fprintf(out, " or \\%s (", name);
break;
case IVL_LO_XOR:
fprintf(out, " xor \\%s (", name);
break;
default:
fprintf(out, "STUB: %s: unsupported gate\n", name);
return -1;
}
draw_nexus(ivl_logic_pin(net, 0));
npins = ivl_logic_pins(net);
for (idx = 1 ; idx < npins ; idx += 1) {
fprintf(out, ", ");
draw_nexus(ivl_logic_pin(net,idx));
}
fprintf(out, ");\n");
return 0;
}
static void edif_show_logic(ivl_net_logic_t net)
{
char jbuf[1024];
unsigned idx;
edif_uref += 1;
switch (ivl_logic_type(net)) {
case IVL_LO_AND:
assert(ivl_logic_pins(net) <= 10);
assert(ivl_logic_pins(net) >= 3);
fprintf(xnf, "(instance (rename U%u \"%s\")",
edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef net"
" (cellRef AND%u (libraryRef VIRTEX))))\n",
ivl_logic_pins(net) - 1);
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
idx-1, edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
}
break;
case IVL_LO_BUF:
assert(ivl_logic_pins(net) == 2);
fprintf(xnf, "(instance (rename U%u \"%s\")",
edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef net"
" (cellRef BUF (libraryRef VIRTEX))))\n");
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
sprintf(jbuf, "(portRef I (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
break;
case IVL_LO_BUFZ:
{
static int bufz_warned_once=0;
if (!bufz_warned_once) {
fprintf (stderr,
"0:0: internal warning: BUFZ objects found "
"in EDIF netlist.\n");
fprintf (stderr,
"0:0: : I'll make BUFs for them.\n");
bufz_warned_once=1;
}
assert(ivl_logic_pins(net) == 2);
fprintf(xnf, "(instance (rename U%u \"%s\")",
edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef net"
" (cellRef BUF (libraryRef VIRTEX))))\n");
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
sprintf(jbuf, "(portRef I (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
}
break;
case IVL_LO_NOR:
assert(ivl_logic_pins(net) <= 10);
assert(ivl_logic_pins(net) >= 3);
fprintf(xnf, "(instance (rename U%u \"%s\")",
edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef net"
" (cellRef NOR%u (libraryRef VIRTEX))))\n",
ivl_logic_pins(net) - 1);
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
idx-1, edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
}
break;
default:
fprintf(stderr, "UNSUPPORT LOGIC TYPE: %u\n", ivl_logic_type(net));
}
}
