IX_STATUS ixParityENAccSwcpPEInit (IxParityENAccInternalCallback ixSwcpPECallback) { /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixSwcpPECallback) { return IX_FAIL; } /* end of if */ /* Register main module internal callback routine */ ixParityENAccSwcpPEConfig.swcpPECallback = ixSwcpPECallback; /* Interrupt Service Routine Info */ ixParityENAccSwcpPEConfig.swcpIsrInfo.swcpInterruptId = IRQ_IXP400_INTC_PARITYENACC_SWCP; ixParityENAccSwcpPEConfig.swcpIsrInfo.swcpIsr = ixParityENAccSwcpPEIsr; /* Install SWCP Interrupt Service Routine */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_SWCP, (IxOsalVoidFnVoidPtr) ixParityENAccSwcpPEIsr, (void *) NULL)) || (IX_SUCCESS != ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_SWCP_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccSwcpPEInit() function */
PUBLIC IX_OSAL_MBUF * ixOsalMbufFree (IX_OSAL_MBUF * bufPtr) { int lock; IX_OSAL_MBUF_POOL *poolPtr; IX_OSAL_MBUF *nextBufPtr = NULL; /* * check parameters */ if (bufPtr == NULL) { ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "ixOsalMbufFree(): " "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); return NULL; } lock = ixOsalIrqLock (); #ifdef IX_OSAL_BUFFER_FREE_PROTECTION /* Prevention for Buffer freed more than once*/ if(!IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr)) { ixOsalIrqUnlock (lock); return NULL; } IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr); #endif poolPtr = IX_OSAL_MBUF_NET_POOL (bufPtr); /* * check the mbuf wrapper signature (if mbuf wrapper was used) */ if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) { IX_OSAL_ENSURE ( (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) == IX_OSAL_MBUF_SYS_SIGNATURE), "ixOsalBuffPoolBufFree: ERROR - Invalid mbuf signature."); } nextBufPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr); IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr) = poolPtr->nextFreeBuf; poolPtr->nextFreeBuf = bufPtr; /* * update the number of free buffers in the pool */ poolPtr->freeBufsInPool++; ixOsalIrqUnlock (lock); return nextBufPtr; }
IX_STATUS ixParityENAccAqmPEInit (IxParityENAccInternalCallback ixAqmPECallback) { UINT32 aqmVirtualBaseAddr = 0; /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixAqmPECallback) { return IX_FAIL; } /* end of if */ /* Memory mapping of the AQM registers */ aqmVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP ( IXP400_PARITYENACC_AQM_BASEADDR, IXP400_PARITYENACC_AQM_MEMMAP_SIZE); if ((UINT32)NULL == aqmVirtualBaseAddr) { return IX_FAIL; } /* end of if */ /* Virtual Addresses assignment for AQM Registers */ ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr = aqmVirtualBaseAddr + IXP400_PARITYENACC_AQM_QUEADDRERR_OFFSET; ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueDataErr = aqmVirtualBaseAddr + IXP400_PARITYENACC_AQM_QUEDATAERR_OFFSET; /* Register main module internal callback routine for AQM */ ixParityENAccAqmPEConfig.aqmPECallback = ixAqmPECallback; /* Interrupt Service Routine Info for AQM for debug purpose */ ixParityENAccAqmPEConfig.aqmIsrInfo.aqmInterruptId = IRQ_IXP400_INTC_PARITYENACC_AQM; ixParityENAccAqmPEConfig.aqmIsrInfo.aqmIsr = ixParityENAccAqmPEIsr; /* Disable parity error detection */ IXP400_PARITYENACC_REG_BIT_CLEAR( ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr, IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_ENABLE | IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_FLAG); /* Install AQM Interrupt Service Routine */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_AQM, (IxOsalVoidFnVoidPtr) ixParityENAccAqmPEIsr, (void *) NULL)) || (IX_SUCCESS != ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); IX_OSAL_MEM_UNMAP(aqmVirtualBaseAddr); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccAqmPEInit() function */
/* * Get a mbuf ptr from the pool */ PUBLIC IX_OSAL_MBUF * ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * poolPtr) { int lock; IX_OSAL_MBUF *newBufPtr = NULL; /* * check parameters */ if (poolPtr == NULL) { ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "ixOsalMbufAlloc(): " "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); return NULL; } lock = ixOsalIrqLock (); newBufPtr = poolPtr->nextFreeBuf; if (newBufPtr) { poolPtr->nextFreeBuf = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr); IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr) = NULL; /* * update the number of free buffers in the pool */ poolPtr->freeBufsInPool--; } else { /* Return NULL to indicate to caller that request is denied. */ ixOsalIrqUnlock (lock); return NULL; } #ifdef IX_OSAL_BUFFER_FREE_PROTECTION /* Set Buffer Used Flag to indicate state.*/ IX_OSAL_MBUF_SET_USED_FLAG(newBufPtr); #endif ixOsalIrqUnlock (lock); return newBufPtr; }
IX_STATUS ixParityENAccPbcPEUnload(void) { UINT32 lockKey; UINT32 status = IX_SUCCESS; IxParityENAccPEConfigOption ixPbcPDCfg; ixPbcPDCfg = IXP400_PARITYENACC_PE_DISABLE; ixParityENAccPbcPEDetectionConfigure(ixPbcPDCfg); /* Unbind the IRQ */ lockKey = ixOsalIrqLock(); if (IX_SUCCESS != ixOsalIrqUnbind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_PBC)) { IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccPbcPEUnload(): "\ "Can't unbind the PBC ISR to IRQ_IXP400_INTC_PARITYENACC_PBC!!!\n",0,0,0,0,0,0); status = IX_FAIL; } ixOsalIrqUnlock(lockKey); /* Unmap the memory */ IX_OSAL_MEM_UNMAP(ixPbcVirtualBaseAddr); return status; } /* end of ixParityENAccPbcPEUnload() function */
IX_STATUS ixQMgrNotificationDisable (IxQMgrQId qId) { int ixQMgrLockKey; #ifndef NDEBUG /* Validate parameters */ if (!ixQMgrQIsConfigured (qId)) { return IX_QMGR_Q_NOT_CONFIGURED; } #endif /* * Enabling interrupts results in Read-Modify-Write * so need critical section */ #ifndef NDEBUG dispatcherStats.queueStats[qId].notificationEnabled = FALSE; #endif ixQMgrLockKey = ixOsalIrqLock(); ixQMgrAqmIfQInterruptDisable (qId); ixOsalIrqUnlock(ixQMgrLockKey); return IX_SUCCESS; }
IX_STATUS ixQMgrDispatcherPrioritySet (IxQMgrQId qId, IxQMgrPriority priority) { int ixQMgrLockKey; if (!ixQMgrQIsConfigured(qId)) { return IX_QMGR_Q_NOT_CONFIGURED; } if (!IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority)) { return IX_QMGR_Q_INVALID_PRIORITY; } ixQMgrLockKey = ixOsalIrqLock(); /* Change priority */ dispatchQInfo[qId].priority = priority; /* Set flag */ rebuildTable = TRUE; ixOsalIrqUnlock(ixQMgrLockKey); #ifndef NDEBUG /* Update statistics */ dispatcherStats.queueStats[qId].priorityChangeCnt++; #endif return IX_SUCCESS; }
PRIVATE void ixAtmmVcQueueClear (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId) { IX_STATUS retval; UINT32 lockKey; lockKey = ixOsalIrqLock(); retval = ixAtmSchVcQueueClear (port, vcId); ixOsalIrqUnlock (lockKey); IX_OSAL_ENSURE(retval == IX_SUCCESS, "Call to ixAtmSchVcQueueClear() failed"); }
/** * @brief adds an ADD or REMOVE event to the main event queue * * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a * record. * * @return IX_ETH_DB_SUCCESS if the event was successfully * sent or IX_ETH_DB_BUSY if the event queue is full * * @internal */ IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry) { UINT32 intLockKey; /* lock interrupts to protect queue */ intLockKey = ixOsalIrqLock(); if (CAN_ENQUEUE(&eventQueue)) { PortEvent *queueEvent = QUEUE_HEAD(&eventQueue); /* update fields on the queue */ ixOsalMemCopy(queueEvent->macAddr.macAddress, macAddr->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); queueEvent->eventType = eventType; queueEvent->portID = portID; queueEvent->staticEntry = staticEntry; PUSH_UPDATE_QUEUE(&eventQueue); /* imcrement event queue semaphore */ ixOsalSemaphorePost(&eventQueueSemaphore); /* unlock interrupts */ ixOsalIrqUnlock(intLockKey); return IX_ETH_DB_SUCCESS; } else /* event queue full */ { /* unlock interrupts */ ixOsalIrqUnlock(intLockKey); return IX_ETH_DB_BUSY; } }
PRIVATE void ixAtmmTxLowHandle (IxAtmLogicalPort port, unsigned maxTxCells) { IxAtmScheduleTable *retTable; IX_STATUS retval; UINT32 lockKey; /* * If we can get the PORT fast mutex it means the port was * UP so can initiate transmission. */ if (IX_ATMM_PORT_MUTEX_TRY_LOCK(port) == IX_SUCCESS) { lockKey = ixOsalIrqLock(); /* * Build a new schedule table * N.B. This is data path so IxAtmSch will validate parameters * rather than do this twice. */ retval = ixAtmSchTableUpdate (port, maxTxCells, &retTable); if (retval == IX_SUCCESS) { /* * Tell Atmd to send the cells in the schedule table. */ retval = ixAtmdAccPortTxProcess (port, retTable); } else { /* * Only other valid retval is QUEUE_EMPTY */ IX_OSAL_ASSERT(retval == IX_ATMSCH_RET_QUEUE_EMPTY); /* * The schedule table is empty so the port has gone * IDLE. Free the BUSY mutex. */ IX_ATMM_TX_MUTEX_UNLOCK(port); } ixOsalIrqUnlock(lockKey); IX_ATMM_PORT_MUTEX_UNLOCK(port); } }
PUBLIC IX_STATUS ixAtmmPortEnable (IxAtmLogicalPort port) { unsigned int maxTxCells; UINT32 lockKey; IX_STATUS retval; retval = ixAtmdAccPortEnable(port); if (retval == IX_SUCCESS) { /* ensure no interrupt is running */ lockKey = ixOsalIrqLock(); retval = ixAtmdAccPortTxFreeEntriesQuery(port, &maxTxCells); if(retval == IX_SUCCESS) { IX_ATMM_PORT_MUTEX_UNLOCK(port); if (maxTxCells == ixAtmmTxQSize[port]) { /* there are no entries in the TX queue, it is necessary to restart the transmission of cells */ ixAtmmTxLowHandle (port, maxTxCells); } else { /* there are cells in the tx queue : the NPE will consume them and this will trigger a tx Low interrupt. The TX traffic will start again */ } } ixOsalIrqUnlock(lockKey); } else if (retval == IX_ATMDACC_WARNING) { /* the port is already up */ retval = IX_SUCCESS; } else { retval = IX_FAIL; } return retval; }
/* * Reuse the received parent LB cell * and modify some of the fields */ PRIVATE IX_STATUS ixOamChildLbCellTx (IxAtmLogicalPort port, IX_OSAL_MBUF *rxMbuf) { IxOamITU610Cell *txCell; IxOamITU610LbPayload *lbPayload; IX_STATUS retval = IX_FAIL; UINT32 lockKey; /* Setup a pointer to the cell data */ txCell = (IxOamITU610Cell *) IX_OSAL_MBUF_MDATA(rxMbuf); /* Setup pointers to Lb fields */ lbPayload = &(txCell->payload.lbPayload); /* Change the loopback indication flag */ IX_OAM_LOOPBACK_INDICATION_SET(lbPayload, IX_OAM_ITU610_LB_INDICATION_CHILD); /* Set the LLID to the CPID */ ixOamMemCpy(lbPayload->llid, oamCpid, IX_OAM_ITU610_LOCATION_ID_LEN); /* flush the mbuf from cache */ ixOamTxFlush( rxMbuf ); /* Transmit the cell, not reentrant on a VC basis so protect */ lockKey = ixOsalIrqLock(); retval = ixOamTxAndRetry (oamTxConnId[port], rxMbuf, 0, /* CLP 0 */ 1); /* Cells per packet */ ixOsalIrqUnlock (lockKey); if (retval == IX_SUCCESS) { /* Increment the loopback out counter */ childLbCellTxCount[port]++; } else { /* Release the MBUF */ ixAtmUtilsMbufFree (rxMbuf); } return retval; }
PUBLIC IX_STATUS ixAtmmPortDisable (IxAtmLogicalPort port) { IX_STATUS retval; UINT32 lockKey; /* ensure no interrupt is running (scheduling and transmission is done under interrupts) */ lockKey = ixOsalIrqLock(); IX_ATMM_PORT_MUTEX_TRY_LOCK(port); /* now, cell transmission is stopped */ ixOsalIrqUnlock(lockKey); /* tell the NPE to stop draining the TX queue */ retval = ixAtmdAccPortDisable(port); if (retval == IX_SUCCESS) { /* wait until a Disable is complete */ while (ixAtmdAccPortDisableComplete(port) == FALSE) { /* since TX done is processing the response, the time to wait is linked to the TxDone polling time */ ixOsalSleep(IX_ATMM_TX_DONE_PERIOD_MSECS/2 ); } } else if (retval == IX_ATMDACC_WARNING) { /* the port is already down */ retval = IX_SUCCESS; } else { retval = IX_FAIL; } IX_ATMM_PORT_MUTEX_UNLOCK(port); return retval; }
PRIVATE void ixNpeMhReceiveIsr (int npeId) { int lockKey; IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " "ixNpeMhReceiveIsr\n"); lockKey = ixOsalIrqLock (); /* invoke the message receive routine to get messages from the NPE */ ixNpeMhReceiveMessagesReceive (npeId); /* update statistical info */ ixNpeMhReceiveStats[npeId].isrs++; ixOsalIrqUnlock (lockKey); IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " "ixNpeMhReceiveIsr\n"); }
IX_STATUS ixParityENAccSwcpPEUnload(void) { UINT32 lockKey; UINT32 status = IX_SUCCESS; IxParityENAccSwcpPEConfigOption ixSwcpPDCfg; ixSwcpPDCfg = IXP400_PARITYENACC_PE_DISABLE; ixParityENAccSwcpPEDetectionConfigure(ixSwcpPDCfg); /* Unbind the IRQ */ lockKey = ixOsalIrqLock(); if (IX_SUCCESS != ixOsalIrqUnbind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_SWCP)) { IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDERR, "ixParityENAccSwcpPEUnload(): "\ "Can't unbind the SWCP ISR to IRQ_IXP400_INTC_PARITYENACC_SWCP!!!\n",0,0,0,0,0,0); status = IX_FAIL; } ixOsalIrqUnlock(lockKey); return status; } /* end of ixParityENAccSwcpPEUnload() function */
PRIVATE IX_STATUS ixAtmmTxDoneHandle (unsigned numOfPdusToProcess, unsigned *reservedPtr) { IX_STATUS retval = IX_SUCCESS; UINT32 lockKey; lockKey = ixOsalIrqLock(); /* Call the Atmd Tx Done API */ retval = ixAtmdAccTxDoneDispatch (numOfPdusToProcess, reservedPtr); ixOsalIrqUnlock(lockKey); if (retval != IX_SUCCESS) { retval = IX_FAIL; } return retval; }
IX_STATUS ixQMgrNotificationEnable (IxQMgrQId qId, IxQMgrSourceId srcSel) { IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */ IxQMgrQStatus qStatusOnExit; /* to this function */ int ixQMgrLockKey; #ifndef NDEBUG if (!ixQMgrQIsConfigured (qId)) { return IX_QMGR_Q_NOT_CONFIGURED; } if ((qId < IX_QMGR_MIN_QUEUPP_QID) && !IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel)) { /* QId 0-31 source id invalid */ return IX_QMGR_INVALID_INT_SOURCE_ID; } if ((IX_QMGR_Q_SOURCE_ID_NE != srcSel) && (qId >= IX_QMGR_MIN_QUEUPP_QID)) { /* * For queues 32-63 the interrupt source is fixed to the Nearly * Empty status flag and therefore should have a srcSel of NE. */ return IX_QMGR_INVALID_INT_SOURCE_ID; } #endif #ifndef NDEBUG dispatcherStats.queueStats[qId].notificationEnabled = TRUE; dispatcherStats.queueStats[qId].srcSel = srcSel; #endif /* Get the current queue status */ ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry); /* * Enabling interrupts results in Read-Modify-Write * so need critical section */ ixQMgrLockKey = ixOsalIrqLock(); /* Calculate the checkMask and checkValue for this q */ ixQMgrAqmIfQStatusCheckValsCalc (qId, srcSel, &dispatchQInfo[qId].statusWordOffset, &dispatchQInfo[qId].statusCheckValue, &dispatchQInfo[qId].statusMask); /* Set the interupt source is this queue is in the range 0-31 */ if (qId < IX_QMGR_MIN_QUEUPP_QID) { ixQMgrAqmIfIntSrcSelWrite (qId, srcSel); } /* Enable the interrupt */ ixQMgrAqmIfQInterruptEnable (qId); ixOsalIrqUnlock(ixQMgrLockKey); /* Get the current queue status */ ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit); /* If the status has changed return a warning */ if (qStatusOnEntry != qStatusOnExit) { return IX_QMGR_WARNING; } return IX_SUCCESS; }
/* * * Transmit loopback parent cell */ PRIVATE IX_STATUS ixOamParentLbCellTx (IxAtmLogicalPort port, UINT32 vpi, UINT32 vci, UINT32 pti) { IxOamITU610Cell *txCell; IxOamITU610LbPayload *lbPayload; IX_OSAL_MBUF *txMbuf; IX_STATUS retval = IX_FAIL; UINT32 lockKey; UINT32 oamHdr = 0x0; /* Get a Tx mbuf */ ixAtmUtilsMbufGet(IX_ATM_OAM_CELL_SIZE_NO_HEC, &txMbuf); if (txMbuf != NULL) { /* set the packet header len */ IX_OSAL_MBUF_PKT_LEN(txMbuf) = IX_OSAL_MBUF_MLEN(txMbuf); txCell = (IxOamITU610Cell *)(IX_OSAL_MBUF_MDATA(txMbuf)); /* Setup shortcut pointers */ lbPayload = &(txCell->payload.lbPayload); /* Set the OAM function type to LB */ IX_OAM_TYPE_AND_FUNC_SET(lbPayload, IX_OAM_ITU610_TYPE_FAULT_MAN_LB); /* Setup the loopback indication */ IX_OAM_LOOPBACK_INDICATION_SET(lbPayload, IX_OAM_ITU610_LB_INDICATION_PARENT); /* Increment the correlation tag and write this into the cell */ lbCorrelationTag++; ixOamMemCpy(lbPayload->correlationTag, (UCHAR *)(&lbCorrelationTag), IX_OAM_ITU610_LB_CORRELATION_TAG_LEN); /* Set Loopback Location Id */ ixOamMemCpy(lbPayload->llid, allOnesLocId, IX_OAM_ITU610_LOCATION_ID_LEN); /* Store the source Id as the CPID */ ixOamMemCpy(lbPayload->sourceId, oamCpid, IX_OAM_ITU610_LOCATION_ID_LEN); /* Set the reserved fields to 0x6a */ ixOamMemSet(lbPayload->reserved, IX_OAM_ITU610_RESERVED_BYTE_VALUE, IX_OAM_ITU610_LB_RESERVED_BYTES_LEN); /* Set the transmit VPI */ IX_OAM_VPI_SET(oamHdr, vpi); /* Set the transmit VCI TX Vci */ IX_OAM_VCI_SET(oamHdr, vci); /* Set the PTI */ IX_OAM_PTI_SET(oamHdr, pti); /* Set the header in buffer */ IX_OAM_HEADER_SET(txCell, oamHdr); /* flush the mbuf frm cache */ ixOamTxFlush( txMbuf ); /* Transmit the cell, not reentrant on a VC basis so protect */ lockKey = ixOsalIrqLock(); retval = ixOamTxAndRetry (oamTxConnId[port], txMbuf, 0, /* CLP 0 */ 1); /* Cells per packet */ ixOsalIrqUnlock (lockKey); if (retval == IX_SUCCESS) { /* Increment the loopback out counter */ parentLbCellTxCount[port]++; } else { /* Release the MBUF */ ixAtmUtilsMbufFree (txMbuf); } } else { IX_OAM_CODELET_IRQ_SAFE_LOG_ERROR("ixOamParentLbCellTx: Failed to get a buffer for transmit"); } return retval; }
PUBLIC IxPerfProfAccStatus ixPerfProfAccXcycleBaselineRun( UINT32 *numBaselineCycle) { int i, priority ; /* task priority. Value is OS dependent */ UINT32 interruptLockKey; UINT32 temp, startTime, /* used to store start time */ stopTime, /* used to store stop time */ duration; /* difference between stop and start time */ #ifdef __vxworks IxOsalThread threadId; IX_STATUS result; #endif /*error check the parameter*/ if (NULL == numBaselineCycle) { /* report the error */ IX_PERFPROF_ACC_LOG( IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR, "ixPerfProfAccXcycleBaselineRun - numBaselineCycle is invalid\n", 0, 0, 0, 0, 0, 0); /* return error */ return IX_PERFPROF_ACC_STATUS_FAIL; } if (IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS == ixPerfProfAccLock()) { return IX_PERFPROF_ACC_STATUS_ANOTHER_UTIL_IN_PROGRESS; } /* * If the tool is running, then do not allow baselining to progress */ if (ixPerfProfAccXcycleMeasurementInProgress) { ixPerfProfAccUnlock(); return IX_PERFPROF_ACC_STATUS_XCYCLE_MEASUREMENT_IN_PROGRESS; } /* * Find out how many loops is needed to to complete * 1/IX_PERFPROF_ACC_XCYCLE_TIME_SLICES_PER_SEC seconds */ ixNumLoopPerTimeSlice= ixPerfProfAccXcycleComputeLoopsPerSlice(); /* * Disable interrupts so that no ISR can run. We get all the CPU * cycles. */ interruptLockKey = ixOsalIrqLock(); #ifdef __linuxapp priority = getpriority(PRIO_PROCESS,0); if(0 != setpriority( PRIO_PROCESS, 0, IX_PERFPROF_ACC_XCYCLE_LINUXAPP_PRIORITY_HIGHEST ) ) { ixPerfProfAccUnlock(); return IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL; } #else result = ixOsalThreadIdGet (&threadId); if (IX_SUCCESS != result) { ixPerfProfAccUnlock(); return IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL; } taskPriorityGet (threadId, &priority); result = ixOsalThreadPrioritySet ( &threadId, IX_PERFPROF_ACC_XCYCLE_VXWORKS_PRIORITY_HIGHEST ); if (IX_SUCCESS != result) { return IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_SET_FAIL; } #endif /* * Perform a measure of time needed for one measurement without * load. */ startTime = ixPerfProfAccXcycleApbTimerGet(); for (i = 0; IX_PERFPROF_ACC_XCYCLE_TIME_SLICES_PER_SEC > i; i++) { temp = ixNumLoopPerTimeSlice; ixPerfProfAccXcycleLoopIter(temp); } stopTime = ixPerfProfAccXcycleApbTimerGet(); /* * Rollover situation is handled through the fact that the different * between start and stop time is a fraction of 32bit storage * The duration of time stored in 32 bits is 65 sec * We expect difference between start and stop time to be * ~ 1 sec */ duration = stopTime - startTime; ixOsalIrqUnlock(interruptLockKey); #ifdef __linuxapp if(setpriority(PRIO_PROCESS, 0, priority) != 0) { ixPerfProfAccUnlock(); return IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL; } #else /* ifdef __linuxapp */ /* * Restore the calling thread to previous priority */ result = ixOsalThreadPrioritySet (&threadId, priority); if (IX_SUCCESS != result) { ixPerfProfAccUnlock(); return IX_PERFPROF_ACC_STATUS_XCYCLE_PRIORITY_RESTORE_FAIL; } #endif /* ifdef __linuxapp */ ixPerfProfAccXcycleCurrentBaseline = duration; *numBaselineCycle = duration; ixPerfProfAccUnlock(); return IX_PERFPROF_ACC_STATUS_SUCCESS ; } /* end of ixPerfProfAccXcycleBaselineRun() */
IX_STATUS ixParityENAccPbcPEInit(IxParityENAccInternalCallback ixPbcPECallback) { UINT32 pbcVirtualBaseAddr = 0; register IxParityENAccPbcPERegisters *pbcPERegisters = &ixParityENAccPbcPEConfig.pbcPERegisters; /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixPbcPECallback) { return IX_FAIL; } /* end of if */ /* Memory mapping of the PBC registers */ if ((UINT32)NULL == (pbcVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP ( IXP400_PARITYENACC_PBC_PCICSR_BASEADDR, IXP400_PARITYENACC_PBC_PCICSR_MEMMAP_SIZE))) { return IX_FAIL; } /* end of if */ ixPbcVirtualBaseAddr = pbcVirtualBaseAddr; /* Virtual Addresses assignment for PBC Control and Status Registers */ pbcPERegisters->pciCrpAdCbe = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_AD_CBE_OFFSET; pbcPERegisters->pciCrpWdata = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_WDATA_OFFSET; pbcPERegisters->pciCrpRdata = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_RDATA_OFFSET; pbcPERegisters->pciCsr = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CSR_OFFSET; pbcPERegisters->pciIsr = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_ISR_OFFSET; pbcPERegisters->pciInten = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_INTEN_OFFSET; /* Register main module internal callback routine */ ixParityENAccPbcPEConfig.pbcPECallback = ixPbcPECallback; /* Interrupt Service Routine Info for debug purpose */ ixParityENAccPbcPEConfig.pbcIsrInfo.pbcInterruptId = IRQ_IXP400_INTC_PARITYENACC_PBC; ixParityENAccPbcPEConfig.pbcIsrInfo.pbcIsr = ixParityENAccPbcPEIsr; /* Disable parity error detection */ /* Write '1' to clear-off the PPE bit */ IXP400_PARITYENACC_REG_BIT_SET( pbcPERegisters->pciIsr, IXP400_PARITYENACC_PBC_ISR_PPE); IXP400_PARITYENACC_REG_BIT_CLEAR( pbcPERegisters->pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE); /* Install PBC Interrupt Service Routine */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_PBC, (IxOsalVoidFnVoidPtr) ixParityENAccPbcPEIsr, (void *) NULL)) || (IX_FAIL == ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); IX_OSAL_MEM_UNMAP(pbcVirtualBaseAddr); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccPbcPEInit() function */
/** * @brief Ethernet event processor loop * * Extracts at most EVENT_PROCESSING_LIMIT batches of events and * sends them for processing to @ref ixEthDBProcessEvent(). * Triggers port updates which normally follow learning events. * * @warning do not call directly, executes in separate thread * * @internal */ IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *unused1) { IxEthDBPortMap triggerPorts; IxEthDBPortId portIndex; ixEthDBEventProcessorRunning = TRUE; IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n"); while (!ixEthDBLearningShutdown) { BOOL keepProcessing = TRUE; UINT32 processedEvents = 0; if (ixEthDBEventProcessorPausing == TRUE) { /* 100 ms*/ ixOsalSleep(100); continue; } IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n"); ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER); IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n"); if (!ixEthDBLearningShutdown) { /* port update handling */ SET_EMPTY_DEPENDENCY_MAP(triggerPorts); while (keepProcessing) { PortEvent local_event; UINT32 intLockKey; /* lock queue */ ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); /* lock NPE interrupts */ intLockKey = ixOsalIrqLock(); /* extract event */ local_event = *(QUEUE_TAIL(&eventQueue)); SHIFT_UPDATE_QUEUE(&eventQueue); ixOsalIrqUnlock(intLockKey); ixOsalMutexUnlock(&eventQueueLock); IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType); ixEthDBProcessEvent(&local_event, triggerPorts); processedEvents++; if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */ || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */ { keepProcessing = FALSE; } } /* Added a pause check here to prevent NPE message * from being sent from ixEthDBUpdatePortLearningTrees() */ while (ixEthDBEventProcessorPausing == TRUE) { /* 100 ms*/ ixOsalSleep(100); } ixEthDBUpdatePortLearningTrees(triggerPorts); } } /* turn off automatic updates */ for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) { ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE; } ixEthDBEventProcessorRunning = FALSE; }
/* * Function definition: ixOsalBuffPoolShow */ PUBLIC void ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * poolPtr) { IX_OSAL_MBUF *nextBufPtr; int count = 0; int lock; /* * check parameters */ if (poolPtr == NULL) { ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, "ixOsalBuffPoolShow(): " "ERROR - Invalid Parameter", 0, 0, 0, 0, 0, 0); /* * return IX_FAIL; */ return; } lock = ixOsalIrqLock (); count = poolPtr->freeBufsInPool; nextBufPtr = poolPtr->nextFreeBuf; ixOsalIrqUnlock (lock); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "=== POOL INFORMATION ===\n", 0, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Pool Name: %s\n", (unsigned int) poolPtr->name, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Pool Allocation Type: %d\n", (unsigned int) poolPtr->poolAllocType, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Pool Mbuf Mem Usage (bytes): %d\n", (unsigned int) poolPtr->mbufMemSize, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Pool Data Mem Usage (bytes): %d\n", (unsigned int) poolPtr->dataMemSize, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Mbuf Data Capacity (bytes): %d\n", (unsigned int) poolPtr->bufDataSize, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Total Mbufs in Pool: %d\n", (unsigned int) poolPtr->totalBufsInPool, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Available Mbufs: %d\n", (unsigned int) count, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Next Available Mbuf: %p\n", (unsigned int) nextBufPtr, 0, 0, 0, 0, 0); if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC) { ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Mbuf Mem Area Start address: %p\n", (unsigned int) poolPtr->mbufMemPtr, 0, 0, 0, 0, 0); ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, "Data Mem Area Start address: %p\n", (unsigned int) poolPtr->dataMemPtr, 0, 0, 0, 0, 0); } }
PRIVATE IX_STATUS ixAtmmVcDemandUpdate (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, unsigned numberOfCells) { IX_STATUS retval = IX_FAIL; IxAtmScheduleTable *retTable; UINT32 lockKey; /* * N.B. Running from a task or interrupt level. * From the task level we could be interrupted * so need to protect VcQueueUpdate, SchTableUpdate * and PortTxProcess */ lockKey = ixOsalIrqLock(); /* * If we can get the PORT fast mutex it means the port was * UP so can initiate transmission. */ if (IX_ATMM_PORT_MUTEX_TRY_LOCK(port) == IX_SUCCESS) { /* * Inform Scheduler of the demand * N.B. This is data path so IxAtmSch will validate parameters * rather than do this twice. */ retval = ixAtmSchVcQueueUpdate (port, vcId, numberOfCells); if( retval == IX_SUCCESS ) { /* * If we can get the BUSY fast mutex it means the port was * IDLE so we need to initiate transmission. */ if (IX_ATMM_TX_MUTEX_TRY_LOCK(port) == IX_SUCCESS) { /* * Build a new schedule table, N.B. system was idle so can potentially * generate a table with ixAtmmTxQSize cells */ retval = ixAtmSchTableUpdate (port, ixAtmmTxQSize[port], &retTable); /* * VcQueueUpdate above placed cells in the scheduler * so the tableUpdate should succeed */ IX_OSAL_ASSERT(retval == IX_SUCCESS); /* * Tell Atmd to send the cells in the schedule table. */ retval = ixAtmdAccPortTxProcess (port, retTable); if ( (retval != IX_SUCCESS) && (retval != IX_ATMDACC_WARNING)) { retval = IX_FAIL; } } } IX_ATMM_PORT_MUTEX_UNLOCK(port); } ixOsalIrqUnlock (lockKey); return retval; }
IX_STATUS ixParityENAccEbcPEInit (IxParityENAccInternalCallback ixEbcPECallback) { UINT32 ebcVirtualBaseAddr = 0; IxParityENAccChipSelectId csId = IXP400_PARITYENACC_PE_EBC_CHIPSEL0; register IxParityENAccEbcPERegisters *ebcPERegisters = &ixParityENAccEbcPEConfig.ebcPERegisters; /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixEbcPECallback) { return IX_FAIL; } /* end of if */ /* Memory mapping of the EBC registers */ if ((UINT32)NULL == (ebcVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP ( IXP400_PARITYENACC_EBC_BASEADDR, IXP400_PARITYENACC_EBC_MEMMAP_SIZE))) { return IX_FAIL; } /* end of if */ /* Virtual Addresses assignment for EBC Registers */ ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL0] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS0_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL1] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS1_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL2] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS2_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL3] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS3_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL4] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS4_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL5] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS5_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL6] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS6_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL7] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS7_OFFSET; ebcPERegisters->expMstControl = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_MST_CONTROL_OFFSET; ebcPERegisters->expParityStatus = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_PARITY_STATUS_OFFSET; /* Register main module internal callback routine */ ixParityENAccEbcPEConfig.ebcPECallback = ixEbcPECallback; /* Interrupt Service Routine Info for debug purpose */ ixParityENAccEbcPEConfig.ebcIsrInfo.ebcInterruptId = IRQ_IXP400_INTC_PARITYENACC_EBC; ixParityENAccEbcPEConfig.ebcIsrInfo.ebcIsr = ixParityENAccEbcPEIsr; /* Disable parity error detection on both Inbound & Outbound interfaces */ for (; csId < IXP400_PARITYENACC_PE_EBC_CHIPSEL_MAX; csId++) { IXP400_PARITYENACC_REG_BIT_CLEAR(ebcPERegisters->expTimingCs[csId], IXP400_PARITYENACC_EBC_TIMING_CSX_PAR_EN); } /* end of for */ IXP400_PARITYENACC_REG_BIT_CLEAR(ebcPERegisters->expMstControl, IXP400_PARITYENACC_EBC_MST_CONTROL_INPAR_EN); /* Install EBC Interrupt Service Routine */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_EBC, (IxOsalVoidFnVoidPtr) ixParityENAccEbcPEIsr, (void *) NULL)) || (IX_SUCCESS != ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); IX_OSAL_MEM_UNMAP(ebcVirtualBaseAddr); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccEbcPEInit() function */
IX_STATUS ixParityENAccMcuPEInit (IxParityENAccInternalCallback ixMcuPECallback) { UINT32 virtualBaseAddr = 0; /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixMcuPECallback) { return IX_FAIL; } /* end of if */ /* Memory mapping of the MCU registers */ if ((UINT32)NULL == (virtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP ( IXP400_PARITYENACC_MCU_BASEADDR, IXP400_PARITYENACC_MCU_MEMMAP_SIZE))) { return IX_FAIL; } /* end of if */ /* Virtual Addresses assignment for MCU Registers */ ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr = virtualBaseAddr + IXP400_PARITYENACC_MCU_ECCR_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuElog0 = virtualBaseAddr + IXP400_PARITYENACC_MCU_ELOG0_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuElog1 = virtualBaseAddr + IXP400_PARITYENACC_MCU_ELOG1_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuEcar0 = virtualBaseAddr + IXP400_PARITYENACC_MCU_ECAR0_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuEcar1 = virtualBaseAddr + IXP400_PARITYENACC_MCU_ECAR1_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuMcisr = virtualBaseAddr + IXP400_PARITYENACC_MCU_MCISR_OFFSET; /* Register main module internal callback routine */ ixParityENAccMcuPEConfig.mcuPECallback = ixMcuPECallback; /* Interrupt Service Routine Info for debug purpose only */ ixParityENAccMcuPEConfig.mcuIsrInfo.mcuInterruptId = IRQ_IXP400_INTC_PARITYENACC_MCU; ixParityENAccMcuPEConfig.mcuIsrInfo.mcuIsr = ixParityENAccMcuPEIsr; /* * Disable parity error detection for both single and multi-bit ECC * and correction of single bit parity using ECC */ IXP400_PARITYENACC_REG_BIT_CLEAR( ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr, IXP400_PARITYENACC_MCU_SBIT_CORRECT_MASK | IXP400_PARITYENACC_MCU_MBIT_REPORT_MASK | IXP400_PARITYENACC_MCU_SBIT_REPORT_MASK); /* Clear off the pending interrupts, if any */ IXP400_PARITYENACC_REG_BIT_SET( ixParityENAccMcuPEConfig.mcuPERegisters.mcuMcisr, IXP400_PARITYENACC_MCU_ERROR0_MASK | IXP400_PARITYENACC_MCU_ERROR1_MASK | IXP400_PARITYENACC_MCU_ERRORN_MASK); /* Install MCU Interrupt Service Routine after disabling the interrupt */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_MCU, (IxOsalVoidFnVoidPtr) ixParityENAccMcuPEIsr, (void *) NULL)) || (IX_SUCCESS != ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); IX_OSAL_MEM_UNMAP (virtualBaseAddr); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccMcuPEInit() function */