Example #1
0
IX_STATUS
ixParityENAccSwcpPEInit (IxParityENAccInternalCallback ixSwcpPECallback)
{
    /* Verify parameters */
    if ((IxParityENAccInternalCallback)NULL == ixSwcpPECallback)
    {
        return IX_FAIL;
    } /* end of if */

    /* Register main module internal callback routine */
    ixParityENAccSwcpPEConfig.swcpPECallback = ixSwcpPECallback;

    /* Interrupt Service Routine Info */
    ixParityENAccSwcpPEConfig.swcpIsrInfo.swcpInterruptId = 
        IRQ_IXP400_INTC_PARITYENACC_SWCP;
    ixParityENAccSwcpPEConfig.swcpIsrInfo.swcpIsr = ixParityENAccSwcpPEIsr;

    /* Install SWCP Interrupt Service Routine */
    {
        INT32 lockKey = ixOsalIrqLock();
        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_SWCP,
                                        (IxOsalVoidFnVoidPtr) ixParityENAccSwcpPEIsr,
                                        (void *) NULL)) ||
            (IX_SUCCESS != ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_SWCP_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnlock(lockKey);
            return IX_FAIL;
        } /* end of if */
        ixOsalIrqUnlock(lockKey);
    }

    return IX_SUCCESS;
} /* end of ixParityENAccSwcpPEInit() function */
Example #2
0
IX_STATUS
ixParityENAccSwcpPEParityInterruptClear (void)
{
    /* Disable the interrupt from triggering further */
    return ixParityENAccIcInterruptDisable(
               IXP400_PARITYENACC_INTC_SWCP_PARITY_INTERRUPT);
} /* end of ixParityENAccSwcpPEParityInterruptClear() function */
Example #3
0
IX_STATUS
ixParityENAccAqmPEInit (IxParityENAccInternalCallback ixAqmPECallback)
{
    UINT32 aqmVirtualBaseAddr = 0;

    /* Verify parameters */
    if ((IxParityENAccInternalCallback)NULL == ixAqmPECallback)
    {
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the AQM registers */
    aqmVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                      IXP400_PARITYENACC_AQM_BASEADDR,
                                      IXP400_PARITYENACC_AQM_MEMMAP_SIZE);
    if ((UINT32)NULL == aqmVirtualBaseAddr)
    {
        return IX_FAIL;
    } /* end of if */

    /* Virtual Addresses assignment for AQM Registers */
    ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr  = 
        aqmVirtualBaseAddr + IXP400_PARITYENACC_AQM_QUEADDRERR_OFFSET;
    ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueDataErr  = 
        aqmVirtualBaseAddr + IXP400_PARITYENACC_AQM_QUEDATAERR_OFFSET;

    /* Register main module internal callback routine for AQM */
    ixParityENAccAqmPEConfig.aqmPECallback = ixAqmPECallback;

    /* Interrupt Service Routine Info for AQM for debug purpose */
    ixParityENAccAqmPEConfig.aqmIsrInfo.aqmInterruptId = 
        IRQ_IXP400_INTC_PARITYENACC_AQM;
    ixParityENAccAqmPEConfig.aqmIsrInfo.aqmIsr = ixParityENAccAqmPEIsr;

    /* Disable parity error detection */
    IXP400_PARITYENACC_REG_BIT_CLEAR(
        ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr,
            IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_ENABLE |
            IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_FLAG);

    /* Install AQM Interrupt Service Routine */
    {
        INT32 lockKey = ixOsalIrqLock();
        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_AQM,
                                        (IxOsalVoidFnVoidPtr) ixParityENAccAqmPEIsr,
                                        (void *) NULL)) ||
            (IX_SUCCESS != ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP(aqmVirtualBaseAddr);
            return IX_FAIL;
        } /* end of if */
        ixOsalIrqUnlock(lockKey);
    }

    return IX_SUCCESS;
} /* end of ixParityENAccAqmPEInit() function */
Example #4
0
IX_STATUS
ixParityENAccAqmPEParityInterruptClear (void)
{
    /* Clear off parity error details */
    IXP400_PARITYENACC_REG_BIT_CLEAR(
        ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr,
            IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_FLAG);

    /* Disable the interrupt from triggering further */
    return ixParityENAccIcInterruptDisable(
               IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT);

} /* end of ixParityENAccAqmPEParityInterruptClear() function */
Example #5
0
IX_STATUS
ixParityENAccSwcpPEDetectionConfigure (
    IxParityENAccSwcpPEConfigOption ixSwcpPDCfg)
{
    if (IXP400_PARITYENACC_PE_ENABLE == ixSwcpPDCfg)
    {
        return ixParityENAccIcInterruptEnable(
                   IXP400_PARITYENACC_INTC_SWCP_PARITY_INTERRUPT);
    }
    else
    {
        return ixParityENAccIcInterruptDisable(
                   IXP400_PARITYENACC_INTC_SWCP_PARITY_INTERRUPT);
    } /* end of if */
} /* end of ixParityENAccSwcpPEDetectionConfigure() function */
Example #6
0
IX_STATUS
ixParityENAccAqmPEDetectionConfigure
    (IxParityENAccAqmPEConfigOption ixAqmPDCfg)
{
    UINT32 aqmPDCfgFlags  = IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_ENABLE;
    UINT32 aqmPDCfgStatus = 0;
    UINT32 aqmTmpPDCfgStatus = 0;

    /* Enable parity error detection */
    if (IXP400_PARITYENACC_PE_ENABLE == ixAqmPDCfg)
    {
        IXP400_PARITYENACC_VAL_BIT_SET(aqmPDCfgStatus, aqmPDCfgFlags);
    } 
    else  /* Disable parity error detection */
    {
        IXP400_PARITYENACC_VAL_BIT_CLEAR(aqmPDCfgStatus, aqmPDCfgFlags);
    } /* end of if */

    /*
     * The following sequence of steps works without the following while loop on Emulator
     * but doesn't work on BMP
     */

    while (TRUE != IXP400_PARITYENACC_VAL_BIT_CHECK(aqmTmpPDCfgStatus, aqmPDCfgStatus))
    {
        /* Set the new configuration */
        IXP400_PARITYENACC_REG_WRITE (
            ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr, aqmPDCfgStatus);

        /* Verify that the configuration is successful or not */
        IXP400_PARITYENACC_REG_READ(
            ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr,&aqmTmpPDCfgStatus);
    }

    if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(aqmTmpPDCfgStatus, aqmPDCfgStatus))
    {
        return (IXP400_PARITYENACC_PE_ENABLE == ixAqmPDCfg) ? 
                    ixParityENAccIcInterruptEnable(
                        IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT) :
                    ixParityENAccIcInterruptDisable(
                        IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT);
    }
    else
    {
        return IX_FAIL;
    } /* end of if */
} /* end of ixParityENAccAqmPEDetectionConfigure() function */
Example #7
0
IX_STATUS
ixParityENAccEbcPEInit (IxParityENAccInternalCallback ixEbcPECallback)
{
    UINT32 ebcVirtualBaseAddr = 0;
    IxParityENAccChipSelectId csId = IXP400_PARITYENACC_PE_EBC_CHIPSEL0;
    register IxParityENAccEbcPERegisters *ebcPERegisters = 
                &ixParityENAccEbcPEConfig.ebcPERegisters;
    
    /* Verify parameters */
    if ((IxParityENAccInternalCallback)NULL == ixEbcPECallback)
    {
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the EBC registers */
    if ((UINT32)NULL == (ebcVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                               IXP400_PARITYENACC_EBC_BASEADDR,
                                               IXP400_PARITYENACC_EBC_MEMMAP_SIZE)))
    {
        return IX_FAIL;
    } /* end of if */

    /* Virtual Addresses assignment for EBC Registers */
    ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL0] = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS0_OFFSET;
    ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL1] = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS1_OFFSET;
    ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL2] = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS2_OFFSET;
    ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL3] = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS3_OFFSET;
    ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL4] = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS4_OFFSET;
    ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL5] = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS5_OFFSET;
    ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL6] = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS6_OFFSET;
    ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL7] = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS7_OFFSET;
    ebcPERegisters->expMstControl = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_MST_CONTROL_OFFSET;
    ebcPERegisters->expParityStatus = 
        ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_PARITY_STATUS_OFFSET;
    
    /* Register main module internal callback routine */
    ixParityENAccEbcPEConfig.ebcPECallback = ixEbcPECallback;

    /* Interrupt Service Routine Info for debug purpose */
    ixParityENAccEbcPEConfig.ebcIsrInfo.ebcInterruptId = 
        IRQ_IXP400_INTC_PARITYENACC_EBC;
    ixParityENAccEbcPEConfig.ebcIsrInfo.ebcIsr = ixParityENAccEbcPEIsr;

    /* Disable parity error detection on both Inbound & Outbound interfaces */
    for (; csId < IXP400_PARITYENACC_PE_EBC_CHIPSEL_MAX; csId++)
    {
        IXP400_PARITYENACC_REG_BIT_CLEAR(ebcPERegisters->expTimingCs[csId],
            IXP400_PARITYENACC_EBC_TIMING_CSX_PAR_EN);
    } /* end of for */
    IXP400_PARITYENACC_REG_BIT_CLEAR(ebcPERegisters->expMstControl,
        IXP400_PARITYENACC_EBC_MST_CONTROL_INPAR_EN);

    /* Install EBC Interrupt Service Routine */
    {
        INT32 lockKey = ixOsalIrqLock();
        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_EBC,
                                        (IxOsalVoidFnVoidPtr) ixParityENAccEbcPEIsr,
                                        (void *) NULL)) ||
            (IX_SUCCESS != ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP(ebcVirtualBaseAddr);
            return IX_FAIL;
        } /* end of if */
        ixOsalIrqUnlock(lockKey);
    }
    return IX_SUCCESS;
} /* end of ixParityENAccEbcPEInit() function */
Example #8
0
IX_STATUS
ixParityENAccEbcPEDetectionConfigure(IxParityENAccEbcPEConfigOption ixEbcPDCfg)
{
    UINT32 ebcPDCfgFlags  = 0;
    UINT32 ebcPDCfgStatus = 0;
    UINT32 ebcTmpPDCfgStatus = 0;
    register IxParityENAccEbcPERegisters *ebcPERegisters = 
                &ixParityENAccEbcPEConfig.ebcPERegisters;

    int loopIdx = 100;

    if (IXP400_PARITYENACC_PE_EBC_CS == ixEbcPDCfg.ebcCsExtSource)
    {
        if (ixEbcPDCfg.ebcCsId >= IXP400_PARITYENACC_PE_EBC_CHIPSEL_MAX)
        {
            return IX_FAIL;
        } /* end of if */

        /* Get current parity detection configuration of Chip Select */
        IXP400_PARITYENACC_REG_READ(
            ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId], &ebcPDCfgStatus);

        /* Enable parity error detection */
        ebcPDCfgFlags  = IXP400_PARITYENACC_EBC_TIMING_CSX_PAR_EN;

        if (IXP400_PARITYENACC_PE_ENABLE == ixEbcPDCfg.ebcInOrOutbound.ebcCsEnabled)
        {
            IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus, ebcPDCfgFlags);
        } 
        else  /* Disable parity error detection */
        {
            IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus, ebcPDCfgFlags);
        } /* end of if */

        while (loopIdx-- && (ebcTmpPDCfgStatus != ebcPDCfgStatus))
        {
            /* Set the new configuration */
            IXP400_PARITYENACC_REG_WRITE(
                ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId], ebcPDCfgStatus);

            /* Configuration successful? */
            IXP400_PARITYENACC_REG_READ(
                ebcPERegisters->expTimingCs[ixEbcPDCfg.ebcCsId],&ebcTmpPDCfgStatus);
        }

        if (ebcTmpPDCfgStatus != ebcPDCfgStatus)
        {
            return IX_FAIL;
        } /* end of if */

        /* 
         * This step required for Even/Odd Parity Type detection from the 
         * EBC Master Control Register if the chip select configuration is
         * specified along with the parity type which is part of the Master
         * Control Register only
         */
        /* Get current parity detection configuration of External Master */
        IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl,&ebcPDCfgStatus);
    } /* else of if */
    else /* EBC Master Control */
    {
        ebcPDCfgFlags  = IXP400_PARITYENACC_EBC_MST_CONTROL_INPAR_EN;

        /* Get current parity detection configuration */
        IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl, &ebcPDCfgStatus);

        /* Enable parity error detection */
        if (IXP400_PARITYENACC_PE_ENABLE == ixEbcPDCfg.ebcInOrOutbound.ebcExtMstEnabled)
        {
            IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus,ebcPDCfgFlags);
        } 
        else  /* Disable parity error detection */
        {
            IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus,ebcPDCfgFlags);
        } /* end of if */
    } /* end of if */

    /* Set Even/Odd parity type */
    ebcPDCfgFlags = IXP400_PARITYENACC_EBC_MST_CONTROL_ODDPARITY;

    if (IXP400_PARITYENACC_PE_ODD_PARITY == ixEbcPDCfg.parityOddEven)
    {
        IXP400_PARITYENACC_VAL_BIT_SET(ebcPDCfgStatus,ebcPDCfgFlags);
    } 
    else  /* Set even parity */
    {
        IXP400_PARITYENACC_VAL_BIT_CLEAR(ebcPDCfgStatus,ebcPDCfgFlags);
    } /* end of if */

    loopIdx = 10;
    while (loopIdx-- && (ebcTmpPDCfgStatus != ebcPDCfgStatus))
    {
        /* Set the new configuration */
        IXP400_PARITYENACC_REG_WRITE(ebcPERegisters->expMstControl, ebcPDCfgStatus);

        /* Configuration successful? */
        IXP400_PARITYENACC_REG_READ(ebcPERegisters->expMstControl,&ebcTmpPDCfgStatus);
    }

    if (ebcTmpPDCfgStatus == ebcPDCfgStatus)
    {
        /* Enable/Disable the corresponding interrupt at Interrupt Controller */
        return ((IXP400_PARITYENACC_PE_ENABLE == 
                    ixEbcPDCfg.ebcInOrOutbound.ebcCsEnabled) ||
                (IXP400_PARITYENACC_PE_ENABLE == 
                    ixEbcPDCfg.ebcInOrOutbound.ebcExtMstEnabled)) ?
                    ixParityENAccIcInterruptEnable( 
                        IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT) :
                    ixParityENAccIcInterruptDisable(
                        IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT);
    }
    else
    {
        IXP400_PARITYENACC_MSGLOG(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDERR,
            "ixParityENAccEbcPEDetectionConfigure(): returned IX_FAIL\n",
            0,0,0,0,0,0);
        return IX_FAIL;
    } /* end of if */
} /* end of ixParityENAccEbcPEDetectionConfigure() function */
Example #9
0
IX_STATUS
ixParityENAccMcuPEInit (IxParityENAccInternalCallback ixMcuPECallback)
{
    UINT32 virtualBaseAddr = 0;

    /* Verify parameters */
    if ((IxParityENAccInternalCallback)NULL == ixMcuPECallback)
    {
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the MCU registers */
    if ((UINT32)NULL == (virtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                            IXP400_PARITYENACC_MCU_BASEADDR,
                                            IXP400_PARITYENACC_MCU_MEMMAP_SIZE)))
    {
        return IX_FAIL;
    } /* end of if */

    /* Virtual Addresses assignment for MCU Registers */
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr  = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ECCR_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuElog0 = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ELOG0_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuElog1 = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ELOG1_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuEcar0 = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ECAR0_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuEcar1 = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_ECAR1_OFFSET;
    ixParityENAccMcuPEConfig.mcuPERegisters.mcuMcisr = 
        virtualBaseAddr + IXP400_PARITYENACC_MCU_MCISR_OFFSET;

    /* Register main module internal callback routine */
    ixParityENAccMcuPEConfig.mcuPECallback = ixMcuPECallback;

    /* Interrupt Service Routine Info for debug purpose only */
    ixParityENAccMcuPEConfig.mcuIsrInfo.mcuInterruptId = 
        IRQ_IXP400_INTC_PARITYENACC_MCU;
    ixParityENAccMcuPEConfig.mcuIsrInfo.mcuIsr = ixParityENAccMcuPEIsr;

    /*
     * Disable parity error detection for both single and multi-bit ECC
     * and correction of single bit parity using ECC
     */
    IXP400_PARITYENACC_REG_BIT_CLEAR(
        ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr,
        IXP400_PARITYENACC_MCU_SBIT_CORRECT_MASK |
        IXP400_PARITYENACC_MCU_MBIT_REPORT_MASK  |
        IXP400_PARITYENACC_MCU_SBIT_REPORT_MASK);

    /* Clear off the pending interrupts, if any */
    IXP400_PARITYENACC_REG_BIT_SET(
        ixParityENAccMcuPEConfig.mcuPERegisters.mcuMcisr,
        IXP400_PARITYENACC_MCU_ERROR0_MASK |
        IXP400_PARITYENACC_MCU_ERROR1_MASK |
        IXP400_PARITYENACC_MCU_ERRORN_MASK);

    /* Install MCU Interrupt Service Routine after disabling the interrupt */
    {
        INT32 lockKey = ixOsalIrqLock();
        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_MCU,
                                        (IxOsalVoidFnVoidPtr) ixParityENAccMcuPEIsr,
                                        (void *) NULL)) ||
            (IX_SUCCESS != ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP (virtualBaseAddr);
            return IX_FAIL;
        } /* end of if */
        ixOsalIrqUnlock(lockKey);
    }
    return IX_SUCCESS;
} /* end of ixParityENAccMcuPEInit() function */
Example #10
0
IX_STATUS 
ixParityENAccMcuPEDetectionConfigure (IxParityENAccMcuPEConfigOption ixMcuPDCfg)
{
    UINT32 mcuPDCfgFlags  = IXP400_PARITYENACC_MCU_ECC_EN_MASK; /* Always to be included */
    UINT32 mcuPDCfgStatus = 0;
    UINT32 mcuTmpPDCfgStatus = 0;

    /*
     * Enable parity error detection for given options
     *
     * - ECC enable
     * - Single-bit ECC error report
     * - Multi-bit ECC error report
     * - Single-bit parity correction using ECC
     */

    /* Enable Single-bit parity error detection */
    if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.singlebitDetectEnabled)
    {
        mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_SBIT_REPORT_MASK;
    } /* end of if */

    /* Enable Single-bit parity error correction */
    if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.singlebitCorrectionEnabled)
    {
        mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_SBIT_CORRECT_MASK;
    } /* end of if */

    /* Enable Multi-bit parity error detection */
    if (IXP400_PARITYENACC_PE_ENABLE == ixMcuPDCfg.multibitDetectionEnabled)
    {
        mcuPDCfgFlags |= IXP400_PARITYENACC_MCU_MBIT_REPORT_MASK;
    } /* end of if */

    /* Check the current ECC feature configuration */
    IXP400_PARITYENACC_REG_READ(ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr,
        &mcuPDCfgStatus);

    /* Existing configuration is same as requested one */
    if (mcuPDCfgStatus == mcuPDCfgFlags)
    {
        return IX_SUCCESS;
    }
    mcuPDCfgStatus = mcuPDCfgFlags;

    IXP400_PARITYENACC_REG_WRITE((ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr),
        mcuPDCfgStatus);

    /* Verify that configuration has been successful or not */
    IXP400_PARITYENACC_REG_READ((ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr),
        &mcuTmpPDCfgStatus);

    if (mcuTmpPDCfgStatus == mcuPDCfgStatus)
    {
        /* Enable/Disable the corresponding interrupt at Interrupt Controller */
        IXP400_PARITYENACC_VAL_BIT_CLEAR(mcuPDCfgFlags,IXP400_PARITYENACC_MCU_ECC_EN_MASK);
        return (0 != mcuPDCfgFlags) ?
                        ixParityENAccIcInterruptEnable( 
                            IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT) :
                        ixParityENAccIcInterruptDisable(
                            IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT);
    }
    else
    {
        return IX_FAIL;
    } /* end of if */
} /* end of ixParityENAccMcuPEDetectionConfigure() function */
Example #11
0
IX_STATUS
ixParityENAccPbcPEInit(IxParityENAccInternalCallback ixPbcPECallback)
{
    UINT32 pbcVirtualBaseAddr = 0;
    register IxParityENAccPbcPERegisters *pbcPERegisters =
        &ixParityENAccPbcPEConfig.pbcPERegisters;
    
    /* Verify parameters */
    if ((IxParityENAccInternalCallback)NULL == ixPbcPECallback)
    {
        return IX_FAIL;
    } /* end of if */

    /* Memory mapping of the PBC registers */
    if ((UINT32)NULL == (pbcVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP (
                                              IXP400_PARITYENACC_PBC_PCICSR_BASEADDR,
                                              IXP400_PARITYENACC_PBC_PCICSR_MEMMAP_SIZE)))
    {
        return IX_FAIL;
    } /* end of if */

    ixPbcVirtualBaseAddr = pbcVirtualBaseAddr;

    /* Virtual Addresses assignment for PBC Control and Status Registers */
    pbcPERegisters->pciCrpAdCbe = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_AD_CBE_OFFSET;
    pbcPERegisters->pciCrpWdata = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_WDATA_OFFSET;
    pbcPERegisters->pciCrpRdata = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_RDATA_OFFSET;
    pbcPERegisters->pciCsr = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CSR_OFFSET;
    pbcPERegisters->pciIsr = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_ISR_OFFSET;
    pbcPERegisters->pciInten = 
        pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_INTEN_OFFSET;

    /* Register main module internal callback routine */
    ixParityENAccPbcPEConfig.pbcPECallback = ixPbcPECallback;

    /* Interrupt Service Routine Info for debug purpose */
    ixParityENAccPbcPEConfig.pbcIsrInfo.pbcInterruptId = 
        IRQ_IXP400_INTC_PARITYENACC_PBC;
    ixParityENAccPbcPEConfig.pbcIsrInfo.pbcIsr = ixParityENAccPbcPEIsr;

    /* Disable parity error detection */

    /* Write '1' to clear-off the PPE bit */
    IXP400_PARITYENACC_REG_BIT_SET(
        pbcPERegisters->pciIsr, IXP400_PARITYENACC_PBC_ISR_PPE);

    IXP400_PARITYENACC_REG_BIT_CLEAR(
        pbcPERegisters->pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE);

    /* Install PBC Interrupt Service Routine */
    {
        INT32 lockKey = ixOsalIrqLock();
        if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_PBC,
                                        (IxOsalVoidFnVoidPtr) ixParityENAccPbcPEIsr,
                                        (void *) NULL)) ||
            (IX_FAIL == ixParityENAccIcInterruptDisable(
                        IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT)))
        {
            ixOsalIrqUnlock(lockKey);
            IX_OSAL_MEM_UNMAP(pbcVirtualBaseAddr);
            return IX_FAIL;
        } /* end of if */
        ixOsalIrqUnlock(lockKey);
    }

    return IX_SUCCESS;
} /* end of ixParityENAccPbcPEInit() function */
Example #12
0
IX_STATUS
ixParityENAccPbcPEDetectionConfigure(IxParityENAccPbcPEConfigOption ixPbcPDCfg)
{
    UINT32 pbcPDCfgStatus = 0;
    UINT32 pbcTmpPDCfgStatus = 0;
    int    loopIdx = 0;

    /* Read the PCI Controller PCI Config SRCR register */
    IXP400_PARITYENACC_REG_WRITE(
        ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
        IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ);
    IXP400_PARITYENACC_REG_READ(
        ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata,
        &pbcPDCfgStatus);

    /* 
     * Set/Clear the PER bit of SRCR register & 
     * Enable/Disable Parity Error Notification
     */
    if (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg)
    {
        /* Set the PER bit of SRCR register */
        IXP400_PARITYENACC_VAL_BIT_SET(pbcPDCfgStatus, 
            IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER);

        /* Enable the PCI Parity Error Interrupt Notification */
        IXP400_PARITYENACC_REG_BIT_SET(
            ixParityENAccPbcPEConfig.pbcPERegisters.pciInten,
            IXP400_PARITYENACC_PBC_INTEN_PPE);
    } 
    /* else of if */
    else
    {
        /* Clear the PER bit of SRCR register */
        IXP400_PARITYENACC_VAL_BIT_CLEAR(pbcPDCfgStatus,
            IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER);

        /* Disable the PCI Parity Error Interrupt Notification */
        IXP400_PARITYENACC_REG_BIT_CLEAR(
            ixParityENAccPbcPEConfig.pbcPERegisters.pciInten,
            IXP400_PARITYENACC_PBC_INTEN_PPE);
    } /* end of if */

    /* Write back the PCI Controller PCI Config SRCR register */
    IXP400_PARITYENACC_REG_WRITE(
        ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
        IXP400_PARITYENACC_PBC_PCICSR_SRCR_WRITE);
    IXP400_PARITYENACC_REG_WRITE(
        ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpWdata,
        pbcPDCfgStatus);

    loopIdx = 10;
    while (loopIdx--)
    {
        /* Verify that the configuration is successful or not */
        IXP400_PARITYENACC_REG_WRITE(
            ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe,
            IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ);
        IXP400_PARITYENACC_REG_READ(
            ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata,
            &pbcTmpPDCfgStatus);
    }

    if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(pbcPDCfgStatus, pbcTmpPDCfgStatus))
    {
        /* Enable/Disable the corresponding interrupt at Interrupt Controller */
        return (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) ?
                    ixParityENAccIcInterruptEnable(
                        IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT) :
                    ixParityENAccIcInterruptDisable(
                        IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT);
    }
    else
    {
        return IX_FAIL;
    } /* end of if */
} /* end of ixParityENAccPbcPEDetectionConfigure() function */