/*
* Configure the specified GPIO pin.
* The clocks on the necessary ports will be enabled automatically.
*
* Returns 0 on success, -EINVAL otherwise.
*/
int kinetis_gpio_config(const struct kinetis_gpio_dsc *dsc, u32 regval)
{
int rv;
/*
* Verify the function arguments
*/
rv = kinetis_validate_gpio(dsc);
if (rv != 0)
goto out;
/*
* Enable the clock on the port we are going to use
*/
rv = kinetis_periph_enable(port_clock_gate[dsc->port], 1);
if (rv != 0)
goto out;
/*
* Configure the pin
*/
KINETIS_PORT(dsc->port)->pcr[dsc->pin] = regval;
rv = 0;
out:
return rv;
}
/*
* Initialize a PIT channel, but do not enable it
*/
static void kinetis_pit_init(unsigned int timer, u32 ticks)
{
volatile struct kinetis_pit_channel_regs *timer_regs =
&KINETIS_PIT->ch[timer];
/*
* Enable power on PIT
*/
kinetis_periph_enable(KINETIS_CG_PIT, 1);
/*
* Enable the PIT module clock
*/
KINETIS_PIT->mcr = 0;
/* Disable the timer and its interrupts */
timer_regs->tctrl = 0;
/* Clear the interrupt for the match channel 0 */
timer_regs->tflg = KINETIS_PIT_TFLG_TIF_MSK;
/* Set the Load Value register */
timer_regs->ldval = ticks;
/* Load the current timer value */
timer_regs->cval = 0;
/* Enable the interrupt for the PIT channel */
timer_regs->tctrl = KINETIS_PIT_TCTRL_TIE_MSK;
}
/*
* Enable or disable an ADC module
*/
static long adc_enable_module(unsigned int mod, int enable)
{
long rv;
volatile struct kinetis_adc_regs *regs;
if (mod >= N_ADC_MODULES) {
rv = -ENODEV;
goto out;
}
spin_lock(&adc_modules[mod].lock);
if (!!adc_modules[mod].enabled == !!enable) {
rv = -EBUSY;
goto unlock;
}
/* Change the recorded state of ADC module */
adc_modules[mod].enabled = enable;
/* Enable or disable the ADC module */
kinetis_periph_enable(kinetis_adc_cg[mod], enable);
if (enable) {
regs = adc_modules[mod].regs;
/* Calibrate the ADC module */
rv = adc_calibrate_module(regs);
if (rv != 0)
goto unlock;
/* Bus clock/4; long sample time */
regs->cfg1 =
KINETIS_ADC_CFG1_ADIV_8 | KINETIS_ADC_CFG1_ADLSMP_MSK |
KINETIS_ADC_CFG1_MODE_16BIT |
KINETIS_ADC_CFG1_ADICLK_BUSCLK;
/* High speed configuration */
regs->cfg2 = KINETIS_ADC_CFG2_ADHSC_MSK;
/* Software triggering; no DMA; disable compare function */
regs->sc2 = 0;
/* Enable 32-sample averaging */
regs->sc3 =
KINETIS_ADC_SC3_AVGE_MSK | KINETIS_ADC_SC3_AVGS_32;
/* Disable PGA */
regs->pga = 0;
}
rv = 0;
unlock:
spin_unlock(&adc_modules[mod].lock);
out:
return rv;
}
/*
* Setup external RAM.
*/
int dram_init(void)
{
#ifdef CONFIG_KINETIS_DDR
/*
* Enable the clock on the DDR module of the MCU
*/
kinetis_periph_enable(KINETIS_CG_DDR, 1);
/*
* Enable DDR pads and set slew rate
*/
KINETIS_SIM->mcr =
KINETIS_SIM_MCR_DDRCFG_DDR2FULL | KINETIS_SIM_MCR_DDRPEN_MSK;
/*
* RCR reset
*/
KINETIS_DDR->rcr |= KINETIS_DDR_RCR_RST_MSK;
/*
* Configure DDR2 SDRAM
*/
KINETIS_DDR->pad_ctrl =
KINETIS_DDR_PAD_CTRL_FIXED_MSK |
KINETIS_DDR_PAD_CTRL_CS0_75 | KINETIS_DDR_PAD_CTRL_DELAY_10BUF;
KINETIS_DDR->cr[0] = KINETIS_DDR_CR00_DDRCLS_DDR2;
KINETIS_DDR->cr[2] =
(KINETIS_DDR_INITAREF << KINETIS_DDR_CR02_INITAREF_BITS) |
(KINETIS_DDR_TINIT << KINETIS_DDR_CR02_TINIT_BITS);
KINETIS_DDR->cr[3] =
(KINETIS_DDR_TCCD << KINETIS_DDR_CR03_TCCD_BITS) |
(KINETIS_DDR_WRLAT << KINETIS_DDR_CR03_WRLAT_BITS) |
(KINETIS_DDR_LATGATE << KINETIS_DDR_CR03_LATGATE_BITS) |
(KINETIS_DDR_LATLIN << KINETIS_DDR_CR03_LATLIN_BITS);
KINETIS_DDR->cr[4] =
(KINETIS_DDR_TRASMIN << KINETIS_DDR_CR04_TRASMIN_BITS) |
(KINETIS_DDR_TRC << KINETIS_DDR_CR04_TRC_BITS) |
(KINETIS_DDR_TRRD << KINETIS_DDR_CR04_TRRD_BITS) |
(KINETIS_DDR_TBINT << KINETIS_DDR_CR04_TBINT_BITS);
KINETIS_DDR->cr[5] =
(KINETIS_DDR_TMRD << KINETIS_DDR_CR05_TMRD_BITS) |
(KINETIS_DDR_TRTP << KINETIS_DDR_CR05_TRTP_BITS) |
(KINETIS_DDR_TRP << KINETIS_DDR_CR05_TRP_BITS) |
(KINETIS_DDR_TWTR << KINETIS_DDR_CR05_TWTR_BITS);
KINETIS_DDR->cr[6] =
(KINETIS_DDR_TRASMAX << KINETIS_DDR_CR06_TRASMAX_BITS) |
(KINETIS_DDR_TMOD << KINETIS_DDR_CR06_TMOD_BITS);
KINETIS_DDR->cr[7] =
KINETIS_DDR_CR07_CCAPEN_MSK |
(KINETIS_DDR_TCKESR << KINETIS_DDR_CR07_TCKESR_BITS) |
(KINETIS_DDR_CLKPW << KINETIS_DDR_CR07_CLKPW_BITS);
KINETIS_DDR->cr[8] =
(KINETIS_DDR_TDAL << KINETIS_DDR_CR08_TDAL_BITS) |
(KINETIS_DDR_TWR << KINETIS_DDR_CR08_TWR_BITS) |
(KINETIS_DDR_TRASDI << KINETIS_DDR_CR08_TRASDI_BITS) |
KINETIS_DDR_CR08_TRAS_MSK;
KINETIS_DDR->cr[9] =
KINETIS_DDR_CR09_BSTLEN_4W |
(KINETIS_DDR_TDLL << KINETIS_DDR_CR09_TDLL_BITS);
KINETIS_DDR->cr[10] =
(KINETIS_DDR_TRPAB << KINETIS_DDR_CR10_TRPAB_BITS) |
(KINETIS_DDR_TCPD << KINETIS_DDR_CR10_TCPD_BITS) |
(KINETIS_DDR_TFAW << KINETIS_DDR_CR10_TFAW_BITS);
KINETIS_DDR->cr[11] =
KINETIS_DDR_CR11_TREFEN_MSK;
KINETIS_DDR->cr[12] =
(KINETIS_DDR_TREF << KINETIS_DDR_CR12_TREF_BITS) |
(KINETIS_DDR_TRFC << KINETIS_DDR_CR12_TRFC_BITS);
KINETIS_DDR->cr[14] =
(KINETIS_DDR_TXSR << KINETIS_DDR_CR14_TXSR_BITS) |
(KINETIS_DDR_TPDEX << KINETIS_DDR_CR14_TPDEX_BITS);
KINETIS_DDR->cr[15] =
(KINETIS_DDR_TXSNR << KINETIS_DDR_CR15_TXSNR_BITS);
KINETIS_DDR->cr[16] = KINETIS_DDR_CR16_QKREF_MSK;
KINETIS_DDR->cr[20] =
(KINETIS_DDR_CKSRX << KINETIS_DDR_CR20_CKSRX_BITS) |
(KINETIS_DDR_CKSRE << KINETIS_DDR_CR20_CKSRE_BITS);
KINETIS_DDR->cr[21] =
(KINETIS_DDR_MR1DAT0 << KINETIS_DDR_CR21_MR1DAT0_BITS) |
(KINETIS_DDR_MR0DAT0 << KINETIS_DDR_CR21_MR0DAT0_BITS);
KINETIS_DDR->cr[22] =
(KINETIS_DDR_MR3DAT0 << KINETIS_DDR_CR22_MR3DAT0_BITS) |
(KINETIS_DDR_MR2DAT0 << KINETIS_DDR_CR22_MR2DAT0_BITS);
KINETIS_DDR->cr[25] =
(KINETIS_DDR_APREBIT << KINETIS_DDR_CR25_APREBIT_BITS) |
(KINETIS_DDR_COLSIZ << KINETIS_DDR_CR25_COLSIZ_BITS) |
(KINETIS_DDR_ADDPINS << KINETIS_DDR_CR25_ADDPINS_BITS) |
KINETIS_DDR_CR25_BNK8_MSK;
KINETIS_DDR->cr[26] =
KINETIS_DDR_CR26_BNKSPT_MSK |
KINETIS_DDR_CR26_ADDCOL_MSK |
(KINETIS_DDR_CMDAGE << KINETIS_DDR_CR26_CMDAGE_BITS) |
(KINETIS_DDR_AGECNT << KINETIS_DDR_CR26_AGECNT_BITS);
KINETIS_DDR->cr[27] =
KINETIS_DDR_CR27_SWPEN_MSK |
KINETIS_DDR_CR27_RWEN_MSK |
KINETIS_DDR_CR27_PRIEN_MSK |
KINETIS_DDR_CR27_PLEN_MSK;
KINETIS_DDR->cr[28] = KINETIS_DDR_CR28_CSMAP_MSK;
KINETIS_DDR->cr[29] = 0;
KINETIS_DDR->cr[30] = KINETIS_DDR_CR30_RSYNCRF_MSK;
KINETIS_DDR->cr[34] =
KINETIS_DDR_CR34_ODTWRCS_MSK |
KINETIS_DDR_CR34_ODTRDC_MSK;
KINETIS_DDR->cr[37] =
(KINETIS_DDR_R2WSAME << KINETIS_DDR_CR37_R2WSAME_BITS);
KINETIS_DDR->cr[38] =
(KINETIS_DDR_P0WRCNT << KINETIS_DDR_CR38_P0WRCNT_BITS);
KINETIS_DDR->cr[39] =
(KINETIS_DDR_WP0 << KINETIS_DDR_CR39_WP0_BITS) |
(KINETIS_DDR_RP0 << KINETIS_DDR_CR39_RP0_BITS) |
(KINETIS_DDR_P0RDCNT << KINETIS_DDR_CR39_P0RDCNT_BITS);
KINETIS_DDR->cr[40] =
(KINETIS_DDR_P1WRCNT << KINETIS_DDR_CR40_P1WRCNT_BITS) |
(KINETIS_DDR_P0TYP << KINETIS_DDR_CR40_P0TYP_BITS);
KINETIS_DDR->cr[41] =
(KINETIS_DDR_WP1 << KINETIS_DDR_CR41_WP1_BITS) |
(KINETIS_DDR_RP1 << KINETIS_DDR_CR41_RP1_BITS) |
(KINETIS_DDR_P1RDCNT << KINETIS_DDR_CR41_P1RDCNT_BITS);
KINETIS_DDR->cr[42] =
(KINETIS_DDR_P2WRCNT << KINETIS_DDR_CR42_P2WRCNT_BITS) |
(KINETIS_DDR_P1TYP << KINETIS_DDR_CR42_P1TYP_BITS);
KINETIS_DDR->cr[43] =
(KINETIS_DDR_WP2 << KINETIS_DDR_CR43_WP2_BITS) |
(KINETIS_DDR_RP2 << KINETIS_DDR_CR43_RP2_BITS) |
(KINETIS_DDR_P2RDCNT << KINETIS_DDR_CR43_P2RDCNT_BITS);
KINETIS_DDR->cr[44] =
(KINETIS_DDR_P2TYP << KINETIS_DDR_CR44_P2TYP_BITS);
KINETIS_DDR->cr[45] =
(KINETIS_DDR_P0PRI3 << KINETIS_DDR_CR45_P0PRI3_BITS) |
(KINETIS_DDR_P0PRI2 << KINETIS_DDR_CR45_P0PRI2_BITS) |
(KINETIS_DDR_P0PRI1 << KINETIS_DDR_CR45_P0PRI1_BITS) |
(KINETIS_DDR_P0PRI0 << KINETIS_DDR_CR45_P0PRI0_BITS);
KINETIS_DDR->cr[46] =
(KINETIS_DDR_P1PRI0 << KINETIS_DDR_CR46_P1PRI0_BITS) |
(KINETIS_DDR_P0PRIRLX << KINETIS_DDR_CR46_P0PRIRLX_BITS) |
(KINETIS_DDR_P0ORD << KINETIS_DDR_CR46_P0ORD_BITS);
KINETIS_DDR->cr[47] =
(KINETIS_DDR_P1ORD << KINETIS_DDR_CR47_P1ORD_BITS) |
(KINETIS_DDR_P1PRI3 << KINETIS_DDR_CR47_P1PRI3_BITS) |
(KINETIS_DDR_P1PRI2 << KINETIS_DDR_CR47_P1PRI2_BITS) |
(KINETIS_DDR_P1PRI1 << KINETIS_DDR_CR47_P1PRI1_BITS);
KINETIS_DDR->cr[48] =
(KINETIS_DDR_P2PRI1 << KINETIS_DDR_CR48_P2PRI1_BITS) |
(KINETIS_DDR_P2PRI0 << KINETIS_DDR_CR48_P2PRI0_BITS) |
(KINETIS_DDR_P1PRIRLX << KINETIS_DDR_CR48_P1PRIRLX_BITS);
KINETIS_DDR->cr[49] =
(KINETIS_DDR_P2ORD << KINETIS_DDR_CR49_P2ORD_BITS) |
(KINETIS_DDR_P2PRI3 << KINETIS_DDR_CR49_P2PRI3_BITS) |
(KINETIS_DDR_P2PRI2 << KINETIS_DDR_CR49_P2PRI2_BITS);
KINETIS_DDR->cr[50] =
(KINETIS_DDR_P2PRIRLX << KINETIS_DDR_CR50_P2PRIRLX_BITS);
KINETIS_DDR->cr[52] =
(KINETIS_DDR_RDDTENBAS << KINETIS_DDR_CR52_RDDTENBAS_BITS) |
(KINETIS_DDR_PHYRDLAT << KINETIS_DDR_CR52_PHYRDLAT_BITS) |
(KINETIS_DDR_PYWRLTBS << KINETIS_DDR_CR52_PYWRLTBS_BITS);
KINETIS_DDR->cr[53] =
(KINETIS_DDR_CTRLUPDMX << KINETIS_DDR_CR53_CTRLUPDMX_BITS);
KINETIS_DDR->cr[54] =
(KINETIS_DDR_PHYUPDTY1 << KINETIS_DDR_CR54_PHYUPDTY1_BITS) |
(KINETIS_DDR_PHYUPDTY0 << KINETIS_DDR_CR54_PHYUPDTY0_BITS);
KINETIS_DDR->cr[55] =
(KINETIS_DDR_PHYUPDTY3 << KINETIS_DDR_CR55_PHYUPDTY3_BITS) |
(KINETIS_DDR_PHYUPDTY2 << KINETIS_DDR_CR55_PHYUPDTY2_BITS);
KINETIS_DDR->cr[56] =
(KINETIS_DDR_WRLATADJ << KINETIS_DDR_CR56_WRLATADJ_BITS) |
(KINETIS_DDR_RDLATADJ << KINETIS_DDR_CR56_RDLATADJ_BITS) |
(KINETIS_DDR_PHYUPDRESP << KINETIS_DDR_CR56_PHYUPDRESP_BITS);
KINETIS_DDR->cr[57] =
KINETIS_DDR_CR57_ODTALTEN_MSK |
(KINETIS_DDR_CLKENDLY << KINETIS_DDR_CR57_CLKENDLY_BITS) |
(KINETIS_DDR_CMDDLY << KINETIS_DDR_CR57_CMDDLY_BITS);
asm("nop");
/*
* Start command processing in the memory controller
*/
KINETIS_DDR->cr[0] |= KINETIS_DDR_CR00_START_MSK;
/*
* Wait for the DRAM to finish initialization
*/
while (!(KINETIS_DDR->cr[30] & KINETIS_DDR_CR30_INTSTAT_DRAMINIT_MSK));
/*
* DDR address size translation
*/
KINETIS_MCM->cr |= KINETIS_MCM_CR_DDRSIZE_128MB;
/*
* Fill in global info with description of DRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
#endif /* CONFIG_KINETIS_DDR */
return 0;
}
