void l2x0_disable_flush()
{
if(l2x0_status())
{
l2x0_disable();
l2x0_clean_all();
l2x0_clean_inv_all();
}
}
void dcache_disable(void)
{
dcache_flush();
#ifndef CONFIG_SYS_NO_DCACHE
cp15_dcache_disable();
#endif
#ifdef CONFIG_CACHE_L2X0
l2x0_disable();
#endif
}
static int mx31_suspend_enter(suspend_state_t state)
{
unsigned long reg;
/* Enable Well Bias and set VSTBY
* VSTBY pin will be asserted during SR mode. This asks the
* PM IC to set the core voltage to the standby voltage
* Must clear the MXC_CCM_CCMR_SBYCS bit as well?? */
reg = __raw_readl(MXC_CCM_CCMR);
reg &= ~MXC_CCM_CCMR_LPM_MASK;
reg |= MXC_CCM_CCMR_WBEN | MXC_CCM_CCMR_VSTBY | MXC_CCM_CCMR_SBYCS;
switch (state) {
case PM_SUSPEND_MEM:
/* State Retention mode */
reg |= 2 << MXC_CCM_CCMR_LPM_OFFSET;
__raw_writel(reg, MXC_CCM_CCMR);
/* Executing CP15 (Wait-for-Interrupt) Instruction */
cpu_do_idle();
break;
case PM_SUSPEND_STANDBY:
/* Deep Sleep Mode */
reg |= 3 << MXC_CCM_CCMR_LPM_OFFSET;
__raw_writel(reg, MXC_CCM_CCMR);
/* wake up by keypad */
reg = __raw_readl(MXC_CCM_WIMR);
reg &= ~(1 << 18);
__raw_writel(reg, MXC_CCM_WIMR);
flush_cache_all();
l2x0_disable();
mxc_pm_arch_entry(MX31_IO_ADDRESS(MX31_NFC_BASE_ADDR), 2048);
printk(KERN_INFO "Resume from DSM\n");
l2x0_enable();
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
break;
default:
return -EINVAL;
}
return 0;
}
