void test_lda()
{
lda_type l1, l2, l3;
double rs;
lda_x_init(&l1, XC_POLARIZED, 3);
lda_init(&l2, XC_LDA_C_PZ, XC_POLARIZED);
lda_init(&l3, XC_LDA_C_VWN, XC_POLARIZED);
for(rs=10; rs>=0.1; rs-=0.01){
double dens, zeta, rho[2];
double ec1, vc1[2], fxc1[4];
double ec2, vc2[2], fxc2[4];
dens = 1.0/(4.0/3.0*M_PI*POW(rs,3));
/* zeta = 1;
rho[0] = dens*(1.0 + zeta)/2.0;
rho[1] = dens*(1.0 - zeta)/2.0; */
rho[0] = dens;
rho[1] = 0;
dens = (rho[0] + rho[1]);
zeta = (rho[0] - rho[1])/dens;
lda(&l2, rho, &ec1, vc1);
lda(&l3, rho, &ec2, vc2);
lda_fxc(&l1, rho, fxc1);
lda_fxc(&l3, rho, fxc2);
printf("%e\t%e\t%e\t%e\t%e\n", dens, fxc1[0], fxc1[1], fxc1[2], fxc1[3]);
}
}
void
viking_cache_enable(void)
{
u_int pcr;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
if ((pcr & VIKING_PCR_ICE) == 0) {
/* I-cache not on; "flash-clear" it now. */
sta(0x80000000, ASI_ICACHECLR, 0); /* Unlock */
sta(0, ASI_ICACHECLR, 0); /* clear */
}
if ((pcr & VIKING_PCR_DCE) == 0) {
/* D-cache not on: "flash-clear" it. */
sta(0x80000000, ASI_DCACHECLR, 0);
sta(0, ASI_DCACHECLR, 0);
}
/* Turn on caches via MMU */
sta(SRMMU_PCR, ASI_SRMMU, pcr | VIKING_PCR_DCE | VIKING_PCR_ICE);
CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
/* Now turn on MultiCache if it exists */
if (cpuinfo.mxcc && CACHEINFO.ec_totalsize > 0) {
/* Set external cache enable bit in MXCC control register */
stda(MXCC_CTRLREG, ASI_CONTROL,
ldda(MXCC_CTRLREG, ASI_CONTROL) | MXCC_CTRLREG_CE);
cpuinfo.flags |= CPUFLG_CACHEPAGETABLES; /* Ok to cache PTEs */
CACHEINFO.ec_enabled = 1;
}
}
void
ms1_cache_enable()
{
u_int pcr;
cache_alias_bits = GUESS_CACHE_ALIAS_BITS;
cache_alias_dist = GUESS_CACHE_ALIAS_DIST;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
/* We "flash-clear" the I/D caches. */
if ((pcr & MS1_PCR_ICE) == 0)
sta(0, ASI_ICACHECLR, 0);
if ((pcr & MS1_PCR_DCE) == 0)
sta(0, ASI_DCACHECLR, 0);
/* Turn on caches */
sta(SRMMU_PCR, ASI_SRMMU, pcr | MS1_PCR_DCE | MS1_PCR_ICE);
cpuinfo.flags |= CPUFLG_CACHEPAGETABLES;
CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
printf("cache enabled\n");
}
void
cypress_cache_enable(void)
{
int i, ls, ts;
u_int pcr;
int alias_dist;
alias_dist = CACHEINFO.c_totalsize;
if (alias_dist > cache_alias_dist) {
cache_alias_dist = alias_dist;
cache_alias_bits = (alias_dist - 1) & ~PGOFSET;
dvma_cachealign = alias_dist;
}
pcr = lda(SRMMU_PCR, ASI_SRMMU);
pcr &= ~CYPRESS_PCR_CM;
/* Now reset cache tag memory if cache not yet enabled */
ls = CACHEINFO.c_linesize;
ts = CACHEINFO.c_totalsize;
if ((pcr & CYPRESS_PCR_CE) == 0)
for (i = 0; i < ts; i += ls)
sta(i, ASI_DCACHETAG, 0);
pcr |= CYPRESS_PCR_CE;
/* If put in write-back mode, turn it on */
if (CACHEINFO.c_vactype == VAC_WRITEBACK)
pcr |= CYPRESS_PCR_CM;
sta(SRMMU_PCR, ASI_SRMMU, pcr);
CACHEINFO.c_enabled = 1;
}
void
swift_cache_enable(void)
{
int i, ls, ts;
u_int pcr;
cache_alias_dist = max(
CACHEINFO.ic_totalsize / CACHEINFO.ic_associativity,
CACHEINFO.dc_totalsize / CACHEINFO.dc_associativity);
cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
/* Now reset cache tag memory if cache not yet enabled */
ls = CACHEINFO.ic_linesize;
ts = CACHEINFO.ic_totalsize;
if ((pcr & SWIFT_PCR_ICE) == 0)
for (i = 0; i < ts; i += ls)
sta(i, ASI_ICACHETAG, 0);
ls = CACHEINFO.dc_linesize;
ts = CACHEINFO.dc_totalsize;
if ((pcr & SWIFT_PCR_DCE) == 0)
for (i = 0; i < ts; i += ls)
sta(i, ASI_DCACHETAG, 0);
pcr |= (SWIFT_PCR_ICE | SWIFT_PCR_DCE);
sta(SRMMU_PCR, ASI_SRMMU, pcr);
CACHEINFO.c_enabled = 1;
}
void
ms1_cache_enable(void)
{
u_int pcr;
cache_alias_dist = max(
CACHEINFO.ic_totalsize / CACHEINFO.ic_associativity,
CACHEINFO.dc_totalsize / CACHEINFO.dc_associativity);
cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
/* We "flash-clear" the I/D caches. */
if ((pcr & MS1_PCR_ICE) == 0)
sta(0, ASI_ICACHECLR, 0);
if ((pcr & MS1_PCR_DCE) == 0)
sta(0, ASI_DCACHECLR, 0);
/* Turn on caches */
sta(SRMMU_PCR, ASI_SRMMU, pcr | MS1_PCR_DCE | MS1_PCR_ICE);
CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
/*
* When zeroing or copying pages, there might still be entries in
* the cache, since we don't flush pages from the cache when
* unmapping them (`vactype' is VAC_NONE). Fortunately, the
* MS1 cache is write-through and not write-allocate, so we can
* use cacheable access while not displacing cache lines.
*/
cpuinfo.flags |= CPUFLG_CACHE_MANDATORY;
}
void
turbosparc_cache_enable(void)
{
int i, ls, ts;
u_int pcr, pcf;
/* External cache sizes in KB; see Turbo sparc manual */
static const int ts_ecache_table[8] = {0,256,512,1024,512,1024,1024,0};
cache_alias_dist = max(
CACHEINFO.ic_totalsize / CACHEINFO.ic_associativity,
CACHEINFO.dc_totalsize / CACHEINFO.dc_associativity);
cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
/* Now reset cache tag memory if cache not yet enabled */
ls = CACHEINFO.ic_linesize;
ts = CACHEINFO.ic_totalsize;
if ((pcr & TURBOSPARC_PCR_ICE) == 0)
for (i = 0; i < ts; i += ls)
sta(i, ASI_ICACHETAG, 0);
ls = CACHEINFO.dc_linesize;
ts = CACHEINFO.dc_totalsize;
if ((pcr & TURBOSPARC_PCR_DCE) == 0)
for (i = 0; i < ts; i += ls)
sta(i, ASI_DCACHETAG, 0);
pcr |= (TURBOSPARC_PCR_ICE | TURBOSPARC_PCR_DCE);
sta(SRMMU_PCR, ASI_SRMMU, pcr);
pcf = lda(SRMMU_PCFG, ASI_SRMMU);
if (pcf & TURBOSPARC_PCFG_SE) {
/*
* Record external cache info. The Turbosparc's second-
* level cache is physically addressed/tagged and is
* not exposed by the PROM.
*/
CACHEINFO.ec_totalsize = 1024 *
ts_ecache_table[(pcf & TURBOSPARC_PCFG_SCC)];
CACHEINFO.ec_linesize = 32;
}
if (pcf & TURBOSPARC_PCFG_SNP)
printf(": DVMA coherent ");
CACHEINFO.c_enabled = 1;
}
Matrix (const MatrixViewType& in) :
nrows_ (in.nrows()),
ncols_ (in.ncols()),
A_ (verified_alloc_size (in.nrows(), in.ncols()))
{
if (A_.size() != 0)
copy_matrix (nrows(), ncols(), get(), lda(), in.get(), in.lda());
}
/// \brief Copy constructor.
///
/// We need an explicit copy constructor, because otherwise the
/// default copy constructor would override the generic matrix
/// view "copy constructor" below.
Matrix (const Matrix& in) :
nrows_ (in.nrows()),
ncols_ (in.ncols()),
A_ (verified_alloc_size (in.nrows(), in.ncols()))
{
if (! in.empty())
copy_matrix (nrows(), ncols(), get(), lda(), in.get(), in.lda());
}
bool operator== (const MatrixViewType& B) const
{
if (get() != B.get() || nrows() != B.nrows() || ncols() != B.ncols() || lda() != B.lda()) {
return false;
} else {
return true;
}
}
static void hposn(void) {
unsigned char msktbl[]={0x81,0x82,0x84,0x88,0x90,0xA0,0xC0};
// F411
ram[HGR_Y]=a;
ram[HGR_X]=x;
ram[HGR_X+1]=y;
pha();
a=a&0xC0;
ram[GBASL]=a;
lsr();
lsr();
a=a|ram[GBASL];
ram[GBASL]=a;
pla();
// F423
ram[GBASH]=a;
asl();
asl();
asl();
rol_mem(GBASH);
asl();
rol_mem(GBASH);
asl();
ror_mem(GBASL);
lda(GBASH);
a=a&0x1f;
a=a|ram[HGR_PAGE];
ram[GBASH]=a;
// F438
a=x;
cpy(0);
if (z==1) goto hposn_2;
y=35;
adc(4);
hposn_1:
iny();
// f442
hposn_2:
sbc(7);
if (c==1) goto hposn_1;
ram[HGR_HORIZ]=y;
x=a;
a=msktbl[(x-0x100)+7]; // LDA MSKTBL-$100+7,X BIT MASK
// MSKTBL=F5B8
ram[HMASK]=a;
a=y;
lsr();
a=ram[HGR_COLOR];
ram[HGR_BITS]=a;
if (c) color_shift();
}
void
hypersparc_cache_enable()
{
int i, ls, ts;
u_int pcr;
ls = CACHEINFO.c_linesize;
ts = CACHEINFO.c_totalsize;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
/*
* First we determine what type of cache we have, and
* setup the anti-aliasing constants appropriately.
*/
if (pcr & HYPERSPARC_PCR_CS) {
cache_alias_bits = CACHE_ALIAS_BITS_HS256k;
cache_alias_dist = CACHE_ALIAS_DIST_HS256k;
} else {
cache_alias_bits = CACHE_ALIAS_BITS_HS128k;
cache_alias_dist = CACHE_ALIAS_DIST_HS128k;
}
/* Now reset cache tag memory if cache not yet enabled */
if ((pcr & HYPERSPARC_PCR_CE) == 0)
for (i = 0; i < ts; i += ls) {
sta(i, ASI_DCACHETAG, 0);
while (lda(i, ASI_DCACHETAG))
sta(i, ASI_DCACHETAG, 0);
}
/* Enable write-back cache */
pcr |= (HYPERSPARC_PCR_CE | HYPERSPARC_PCR_CM);
sta(SRMMU_PCR, ASI_SRMMU, pcr);
CACHEINFO.c_enabled = 1;
/* XXX: should add support */
if (CACHEINFO.c_hwflush)
panic("cache_enable: can't handle 4M with hw-flush cache");
printf("cache enabled\n");
}
void
turbosparc_cache_enable()
{
int i, ls, ts;
u_int pcr, pcf;
cache_alias_dist = max(
CACHEINFO.ic_totalsize / CACHEINFO.ic_associativity,
CACHEINFO.dc_totalsize / CACHEINFO.dc_associativity);
cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
/* Now reset cache tag memory if cache not yet enabled */
ls = CACHEINFO.ic_linesize;
ts = CACHEINFO.ic_totalsize;
if ((pcr & TURBOSPARC_PCR_ICE) == 0)
for (i = 0; i < ts; i += ls)
sta(i, ASI_ICACHETAG, 0);
ls = CACHEINFO.dc_linesize;
ts = CACHEINFO.dc_totalsize;
if ((pcr & TURBOSPARC_PCR_DCE) == 0)
for (i = 0; i < ts; i += ls) {
sta(i, ASI_DCACHETAG, 0);
while (lda(i, ASI_DCACHETAG))
sta(i, ASI_DCACHETAG, 0);
}
pcr |= (TURBOSPARC_PCR_ICE | TURBOSPARC_PCR_DCE);
sta(SRMMU_PCR, ASI_SRMMU, pcr);
pcf = lda(SRMMU_PCFG, ASI_SRMMU);
if (pcf & TURBOSPARC_PCFG_SNP)
printf("DVMA coherent ");
CACHEINFO.c_enabled = 1;
printf("cache enabled\n");
}
static char * LDA2() {
//load neg val into accumulator
CPU *c = getCPU();
int8_t operand = -99;
OP_CODE_INFO *o = getOP_CODE_INFO(operand,0,modeImmediate);
lda(c,o);
int8_t accumVal = getRegByte(c,ACCUM);
mu_assert("LDA2 err, ACCUM reg != -99", accumVal == -99);
mu_run_test_with_args(testRegStatus,c,"10100000",
" NVUBDIZC NVUBDIZC\nCLC1 err, %s != %s");
freeOP_CODE_INFO(o);
free(c);
return 0;
}
void
swift_cache_enable()
{
int i, ls, ts;
u_int pcr;
cache_alias_dist = max(
CACHEINFO.ic_totalsize / CACHEINFO.ic_associativity,
CACHEINFO.dc_totalsize / CACHEINFO.dc_associativity);
cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
pcr |= (SWIFT_PCR_ICE | SWIFT_PCR_DCE);
sta(SRMMU_PCR, ASI_SRMMU, pcr);
/* Now reset cache tag memory if cache not yet enabled */
ls = CACHEINFO.ic_linesize;
ts = CACHEINFO.ic_totalsize;
if ((pcr & SWIFT_PCR_ICE) == 0)
for (i = 0; i < ts; i += ls)
sta(i, ASI_ICACHETAG, 0);
ls = CACHEINFO.dc_linesize;
ts = CACHEINFO.dc_totalsize;
if ((pcr & SWIFT_PCR_DCE) == 0)
for (i = 0; i < ts; i += ls) {
sta(i, ASI_DCACHETAG, 0);
while (lda(i, ASI_DCACHETAG))
sta(i, ASI_DCACHETAG, 0);
}
/* XXX - assume that an MS2 with ecache is really a turbo in disguise */
if (CACHEINFO.ec_totalsize == 0)
cpuinfo.flags |= CPUFLG_CACHEPAGETABLES; /* Ok to cache PTEs */
CACHEINFO.c_enabled = 1;
printf("cache enabled\n");
}
void
cypress_cache_enable()
{
int i, ls, ts;
u_int pcr;
cache_alias_dist = CACHEINFO.c_totalsize;
cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
pcr &= ~(CYPRESS_PCR_CE | CYPRESS_PCR_CM);
/* Now reset cache tag memory if cache not yet enabled */
ls = CACHEINFO.c_linesize;
ts = CACHEINFO.c_totalsize;
if ((pcr & CYPRESS_PCR_CE) == 0)
for (i = 0; i < ts; i += ls) {
sta(i, ASI_DCACHETAG, 0);
while (lda(i, ASI_DCACHETAG))
sta(i, ASI_DCACHETAG, 0);
}
pcr |= CYPRESS_PCR_CE;
#if 1
pcr &= ~CYPRESS_PCR_CM; /* XXX Disable write-back mode */
#else
/* If put in write-back mode, turn it on */
if (CACHEINFO.c_vactype == VAC_WRITEBACK)
pcr |= CYPRESS_PCR_CM;
#endif
sta(SRMMU_PCR, ASI_SRMMU, pcr);
CACHEINFO.c_enabled = 1;
printf("cache enabled\n");
}
void
hypersparc_cache_enable(void)
{
int i, ls, ts;
u_int pcr, v;
int alias_dist;
/*
* Setup the anti-aliasing constants and DVMA alignment constraint.
*/
alias_dist = CACHEINFO.c_totalsize;
if (alias_dist > cache_alias_dist) {
cache_alias_dist = alias_dist;
cache_alias_bits = (alias_dist - 1) & ~PGOFSET;
dvma_cachealign = cache_alias_dist;
}
ls = CACHEINFO.c_linesize;
ts = CACHEINFO.c_totalsize;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
/* Now reset cache tag memory if cache not yet enabled */
if ((pcr & HYPERSPARC_PCR_CE) == 0)
for (i = 0; i < ts; i += ls)
sta(i, ASI_DCACHETAG, 0);
pcr &= ~(HYPERSPARC_PCR_CE | HYPERSPARC_PCR_CM);
hypersparc_cache_flush_all();
/* Enable write-back cache */
pcr |= HYPERSPARC_PCR_CE;
if (CACHEINFO.c_vactype == VAC_WRITEBACK)
pcr |= HYPERSPARC_PCR_CM;
sta(SRMMU_PCR, ASI_SRMMU, pcr);
CACHEINFO.c_enabled = 1;
/* XXX: should add support */
if (CACHEINFO.c_hwflush)
panic("cache_enable: can't handle 4M with hw-flush cache");
/*
* Enable instruction cache and, on single-processor machines,
* disable `Unimplemented Flush Traps'.
*/
v = HYPERSPARC_ICCR_ICE | (sparc_ncpus <= 1 ? HYPERSPARC_ICCR_FTD : 0);
wrasr(v, HYPERSPARC_ASRNUM_ICCR);
}
void interpret_packet(void) {
int size = rx(); // ignore. protocol is self-terminating.
(void)size;
int command = rx();
switch(command & 0x0F) {
default:
case 0: ack(); break;
case 1: npush(); break;
case 2: npop(); break;
case 3: jsr(); break;
case 4: lda(); break;
case 5: ldf(); break;
case 7: intr(); break;
case 8: nafetch(); break;
case 9: nffetch(); break;
case 10: nastore(); break;
case 11: nfstore(); break;
}
infof("\n");
}
void
viking_cache_enable()
{
u_int pcr;
cache_alias_dist = max(
CACHEINFO.ic_totalsize / CACHEINFO.ic_associativity,
CACHEINFO.dc_totalsize / CACHEINFO.dc_associativity);
cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
pcr = lda(SRMMU_PCR, ASI_SRMMU);
if ((pcr & VIKING_PCR_ICE) == 0) {
/* I-cache not on; "flash-clear" it now. */
sta(0x80000000, ASI_ICACHECLR, 0); /* Unlock */
sta(0, ASI_ICACHECLR, 0); /* clear */
}
if ((pcr & VIKING_PCR_DCE) == 0) {
/* D-cache not on: "flash-clear" it. */
sta(0x80000000, ASI_DCACHECLR, 0);
sta(0, ASI_DCACHECLR, 0);
}
/* Turn on caches via MMU */
sta(SRMMU_PCR, ASI_SRMMU, pcr | VIKING_PCR_DCE | VIKING_PCR_ICE);
CACHEINFO.c_enabled = CACHEINFO.dc_enabled = 1;
/* Now turn on MultiCache if it exists */
if (cpuinfo.mxcc && CACHEINFO.ec_totalsize > 0) {
/* Multicache controller */
stda(MXCC_ENABLE_ADDR, ASI_CONTROL,
ldda(MXCC_ENABLE_ADDR, ASI_CONTROL) |
(u_int64_t)MXCC_ENABLE_BIT);
cpuinfo.flags |= CPUFLG_CACHEPAGETABLES; /* Ok to cache PTEs */
CACHEINFO.ec_enabled = 1;
}
printf("cache enabled\n");
}
/**
* @brief emulate instruction
* @return returns false if something goes wrong (e.g. illegal instruction)
*
* Current limitations:
*
* - Illegal instructions are not implemented
* - Excess cycles due to page boundary crossing are not calculated
* - Some known architectural bugs are not emulated
*/
bool Cpu::emulate()
{
/* fetch instruction */
uint8_t insn = fetch_op();
bool retval = true;
/* emulate instruction */
switch(insn)
{
/* BRK */
case 0x0: brk(); break;
/* ORA (nn,X) */
case 0x1: ora(load_byte(addr_indx()),6); break;
/* ORA nn */
case 0x5: ora(load_byte(addr_zero()),3); break;
/* ASL nn */
case 0x6: asl_mem(addr_zero(),5); break;
/* PHP */
case 0x8: php(); break;
/* ORA #nn */
case 0x9: ora(fetch_op(),2); break;
/* ASL A */
case 0xA: asl_a(); break;
/* ORA nnnn */
case 0xD: ora(load_byte(addr_abs()),4); break;
/* ASL nnnn */
case 0xE: asl_mem(addr_abs(),6); break;
/* BPL nn */
case 0x10: bpl(); break;
/* ORA (nn,Y) */
case 0x11: ora(load_byte(addr_indy()),5); break;
/* ORA nn,X */
case 0x15: ora(load_byte(addr_zerox()),4); break;
/* ASL nn,X */
case 0x16: asl_mem(addr_zerox(),6); break;
/* CLC */
case 0x18: clc(); break;
/* ORA nnnn,Y */
case 0x19: ora(load_byte(addr_absy()),4); break;
/* ORA nnnn,X */
case 0x1D: ora(load_byte(addr_absx()),4); break;
/* ASL nnnn,X */
case 0x1E: asl_mem(addr_absx(),7); break;
/* JSR */
case 0x20: jsr(); break;
/* AND (nn,X) */
case 0x21: _and(load_byte(addr_indx()),6); break;
/* BIT nn */
case 0x24: bit(addr_zero(),3); break;
/* AND nn */
case 0x25: _and(load_byte(addr_zero()),3); break;
/* ROL nn */
case 0x26: rol_mem(addr_zero(),5); break;
/* PLP */
case 0x28: plp(); break;
/* AND #nn */
case 0x29: _and(fetch_op(),2); break;
/* ROL A */
case 0x2A: rol_a(); break;
/* BIT nnnn */
case 0x2C: bit(addr_abs(),4); break;
/* AND nnnn */
case 0x2D: _and(load_byte(addr_abs()),4); break;
/* ROL nnnn */
case 0x2E: rol_mem(addr_abs(),6); break;
/* BMI nn */
case 0x30: bmi(); break;
/* AND (nn,Y) */
case 0x31: _and(load_byte(addr_indy()),5); break;
/* AND nn,X */
case 0x35: _and(load_byte(addr_zerox()),4); break;
/* ROL nn,X */
case 0x36: rol_mem(addr_zerox(),6); break;
/* SEC */
case 0x38: sec(); break;
/* AND nnnn,Y */
case 0x39: _and(load_byte(addr_absy()),4); break;
/* AND nnnn,X */
case 0x3D: _and(load_byte(addr_absx()),4); break;
/* ROL nnnn,X */
case 0x3E: rol_mem(addr_absx(),7); break;
/* RTI */
case 0x40: rti(); break;
/* EOR (nn,X) */
case 0x41: eor(load_byte(addr_indx()),6); break;
/* EOR nn */
case 0x45: eor(load_byte(addr_zero()),3); break;
/* LSR nn */
case 0x46: lsr_mem(addr_zero(),5); break;
/* PHA */
case 0x48: pha(); break;
/* EOR #nn */
case 0x49: eor(fetch_op(),2); break;
/* BVC */
case 0x50: bvc(); break;
/* JMP nnnn */
case 0x4C: jmp(); break;
/* EOR nnnn */
case 0x4D: eor(load_byte(addr_abs()),4); break;
/* LSR A */
case 0x4A: lsr_a(); break;
/* LSR nnnn */
case 0x4E: lsr_mem(addr_abs(),6); break;
/* EOR (nn,Y) */
case 0x51: eor(load_byte(addr_indy()),5); break;
/* EOR nn,X */
case 0x55: eor(load_byte(addr_zerox()),4); break;
/* LSR nn,X */
case 0x56: lsr_mem(addr_zerox(),6); break;
/* CLI */
case 0x58: cli(); break;
/* EOR nnnn,Y */
case 0x59: eor(load_byte(addr_absy()),4); break;
/* EOR nnnn,X */
case 0x5D: eor(load_byte(addr_absx()),4); break;
/* LSR nnnn,X */
case 0x5E: lsr_mem(addr_absx(),7); break;
/* RTS */
case 0x60: rts(); break;
/* ADC (nn,X) */
case 0x61: adc(load_byte(addr_indx()),6); break;
/* ADC nn */
case 0x65: adc(load_byte(addr_zero()),3); break;
/* ROR nn */
case 0x66: ror_mem(addr_zero(),5); break;
/* PLA */
case 0x68: pla(); break;
/* ADC #nn */
case 0x69: adc(fetch_op(),2); break;
/* ROR A */
case 0x6A: ror_a(); break;
/* JMP (nnnn) */
case 0x6C: jmp_ind(); break;
/* ADC nnnn */
case 0x6D: adc(load_byte(addr_abs()),4); break;
/* ROR nnnn */
case 0x6E: ror_mem(addr_abs(),6); break;
/* BVS */
case 0x70: bvs(); break;
/* ADC (nn,Y) */
case 0x71: adc(load_byte(addr_indy()),5); break;
/* ADC nn,X */
case 0x75: adc(load_byte(addr_zerox()),4); break;
/* ROR nn,X */
case 0x76: ror_mem(addr_zerox(),6); break;
/* SEI */
case 0x78: sei(); break;
/* ADC nnnn,Y */
case 0x79: adc(load_byte(addr_absy()),4); break;
/* ADC nnnn,X */
case 0x7D: adc(load_byte(addr_absx()),4); break;
/* ROR nnnn,X */
case 0x7E: ror_mem(addr_absx(),7); break;
/* STA (nn,X) */
case 0x81: sta(addr_indx(),6); break;
/* STY nn */
case 0x84: sty(addr_zero(),3); break;
/* STA nn */
case 0x85: sta(addr_zero(),3); break;
/* STX nn */
case 0x86: stx(addr_zero(),3); break;
/* DEY */
case 0x88: dey(); break;
/* TXA */
case 0x8A: txa(); break;
/* STY nnnn */
case 0x8C: sty(addr_abs(),4); break;
/* STA nnnn */
case 0x8D: sta(addr_abs(),4); break;
/* STX nnnn */
case 0x8E: stx(addr_abs(),4); break;
/* BCC nn */
case 0x90: bcc(); break;
/* STA (nn,Y) */
case 0x91: sta(addr_indy(),6); break;
/* STY nn,X */
case 0x94: sty(addr_zerox(),4); break;
/* STA nn,X */
case 0x95: sta(addr_zerox(),4); break;
/* STX nn,Y */
case 0x96: stx(addr_zeroy(),4); break;
/* TYA */
case 0x98: tya(); break;
/* STA nnnn,Y */
case 0x99: sta(addr_absy(),5); break;
/* TXS */
case 0x9A: txs(); break;
/* STA nnnn,X */
case 0x9D: sta(addr_absx(),5); break;
/* LDY #nn */
case 0xA0: ldy(fetch_op(),2); break;
/* LDA (nn,X) */
case 0xA1: lda(load_byte(addr_indx()),6); break;
/* LDX #nn */
case 0xA2: ldx(fetch_op(),2); break;
/* LDY nn */
case 0xA4: ldy(load_byte(addr_zero()),3); break;
/* LDA nn */
case 0xA5: lda(load_byte(addr_zero()),3); break;
/* LDX nn */
case 0xA6: ldx(load_byte(addr_zero()),3); break;
/* TAY */
case 0xA8: tay(); break;
/* LDA #nn */
case 0xA9: lda(fetch_op(),2); break;
/* TAX */
case 0xAA: tax(); break;
/* LDY nnnn */
case 0xAC: ldy(load_byte(addr_abs()),4); break;
/* LDA nnnn */
case 0xAD: lda(load_byte(addr_abs()),4); break;
/* LDX nnnn */
case 0xAE: ldx(load_byte(addr_abs()),4); break;
/* BCS nn */
case 0xB0: bcs(); break;
/* LDA (nn,Y) */
case 0xB1: lda(load_byte(addr_indy()),5); break;
/* LDY nn,X */
case 0xB4: ldy(load_byte(addr_zerox()),3); break;
/* LDA nn,X */
case 0xB5: lda(load_byte(addr_zerox()),3); break;
/* LDX nn,Y */
case 0xB6: ldx(load_byte(addr_zeroy()),3); break;
/* CLV */
case 0xB8: clv(); break;
/* LDA nnnn,Y */
case 0xB9: lda(load_byte(addr_absy()),4); break;
/* TSX */
case 0xBA: tsx(); break;
/* LDY nnnn,X */
case 0xBC: ldy(load_byte(addr_absx()),4); break;
/* LDA nnnn,X */
case 0xBD: lda(load_byte(addr_absx()),4); break;
/* LDX nnnn,Y */
case 0xBE: ldx(load_byte(addr_absy()),4); break;
/* CPY #nn */
case 0xC0: cpy(fetch_op(),2); break;
/* CMP (nn,X) */
case 0xC1: cmp(load_byte(addr_indx()),6); break;
/* CPY nn */
case 0xC4: cpy(load_byte(addr_zero()),3); break;
/* CMP nn */
case 0xC5: cmp(load_byte(addr_zero()),3); break;
/* DEC nn */
case 0xC6: dec(addr_zero(),5); break;
/* INY */
case 0xC8: iny(); break;
/* CMP #nn */
case 0xC9: cmp(fetch_op(),2); break;
/* DEX */
case 0xCA: dex(); break;
/* CPY nnnn */
case 0xCC: cpy(load_byte(addr_abs()),4); break;
/* CMP nnnn */
case 0xCD: cmp(load_byte(addr_abs()),4); break;
/* DEC nnnn */
case 0xCE: dec(addr_abs(),6); break;
/* BNE nn */
case 0xD0: bne(); break;
/* CMP (nn,Y) */
case 0xD1: cmp(load_byte(addr_indy()),5); break;
/* CMP nn,X */
case 0xD5: cmp(load_byte(addr_zerox()),4); break;
/* DEC nn,X */
case 0xD6: dec(addr_zerox(),6); break;
/* CLD */
case 0xD8: cld(); break;
/* CMP nnnn,Y */
case 0xD9: cmp(load_byte(addr_absy()),4); break;
/* CMP nnnn,X */
case 0xDD: cmp(load_byte(addr_absx()),4); break;
/* DEC nnnn,X */
case 0xDE: dec(addr_absx(),7); break;
/* CPX #nn */
case 0xE0: cpx(fetch_op(),2); break;
/* SBC (nn,X) */
case 0xE1: sbc(load_byte(addr_indx()),6); break;
/* CPX nn */
case 0xE4: cpx(load_byte(addr_zero()),3); break;
/* SBC nn */
case 0xE5: sbc(load_byte(addr_zero()),3); break;
/* INC nn */
case 0xE6: inc(addr_zero(),5); break;
/* INX */
case 0xE8: inx(); break;
/* SBC #nn */
case 0xE9: sbc(fetch_op(),2); break;
/* NOP */
case 0xEA: nop(); break;
/* CPX nnnn */
case 0xEC: cpx(load_byte(addr_abs()),4); break;
/* SBC nnnn */
case 0xED: sbc(load_byte(addr_abs()),4); break;
/* INC nnnn */
case 0xEE: inc(addr_abs(),6); break;
/* BEQ nn */
case 0xF0: beq(); break;
/* SBC (nn,Y) */
case 0xF1: sbc(load_byte(addr_indy()),5); break;
/* SBC nn,X */
case 0xF5: sbc(load_byte(addr_zerox()),4); break;
/* INC nn,X */
case 0xF6: inc(addr_zerox(),6); break;
/* SED */
case 0xF8: sed(); break;
/* SBC nnnn,Y */
case 0xF9: sbc(load_byte(addr_absy()),4); break;
/* SBC nnnn,X */
case 0xFD: sbc(load_byte(addr_absx()),4); break;
/* INC nnnn,X */
case 0xFE: inc(addr_absx(),7); break;
/* Unknown or illegal instruction */
default:
D("Unknown instruction: %X at %04x\n", insn,pc());
retval = false;
}
return retval;
}
static void move_up_or_down(void) {
// F4D3
if (n==1) goto move_down;
c=0;
lda(GBASH);
bit(0x1c); // CON.1C
if (z!=1) goto mu_5;
asl_mem(GBASL);
if (c==1) goto mu_3;
bit(0x03); // CON.03
if (z==1) goto mu_1;
adc(0x1f);
c=1;
goto mu_4;
// F4Eb
mu_1:
adc(0x23);
pha();
lda(GBASL);
adc(0xb0);
if (c==1) goto mu_2;
adc(0xf0);
// f4f6
mu_2:
ram[GBASL]=a;
pla();
goto mu_4;
mu_3:
adc(0x1f);
mu_4:
ror_mem(GBASL);
mu_5:
adc(0xfc);
ud_1:
ram[GBASH]=a;
return;
// f505
move_down:
lda(GBASH);
adc(4);
bit(0x1c);
if (z!=1) goto ud_1;
asl_mem(GBASL);
if (c==0) goto md_2;
adc(0xe0);
c=0;
bit(0x4);
if (z==1) goto md_3;
lda(GBASL);
adc(0x50);
a=a^0xf0;
if (a==0) goto md_1;
a=a^0xf0;
md_1:
ram[GBASL]=a;
lda(HGR_PAGE);
goto md_3;
md_2:
adc(0xe0);
md_3:
ror_mem(GBASL);
goto ud_1;
}
/// \brief Const reference to element (i,j) of the matrix.
///
/// \param i [in] Zero-based row index of the matrix.
/// \param j [in] Zero-based column index of the matrix.
const Scalar& operator() (const Ordinal i, const Ordinal j) const {
return A_[i + j*lda()];
}
//------------------------------------------------------------------------------
// Fisherfaces
//------------------------------------------------------------------------------
void Fisherfaces::train(InputArrayOfArrays src, InputArray _lbls) {
if(src.total() == 0) {
String error_message = format("Empty training data was given. You'll need more than one sample to learn a model.");
CV_Error(Error::StsBadArg, error_message);
} else if(_lbls.getMat().type() != CV_32SC1) {
String error_message = format("Labels must be given as integer (CV_32SC1). Expected %d, but was %d.", CV_32SC1, _lbls.type());
CV_Error(Error::StsBadArg, error_message);
}
// make sure data has correct size
if(src.total() > 1) {
for(int i = 1; i < static_cast<int>(src.total()); i++) {
if(src.getMat(i-1).total() != src.getMat(i).total()) {
String error_message = format("In the Fisherfaces method all input samples (training images) must be of equal size! Expected %d pixels, but was %d pixels.", src.getMat(i-1).total(), src.getMat(i).total());
CV_Error(Error::StsUnsupportedFormat, error_message);
}
}
}
// get data
Mat labels = _lbls.getMat();
Mat data = asRowMatrix(src, CV_64FC1);
// number of samples
int N = data.rows;
// make sure labels are passed in correct shape
if(labels.total() != (size_t) N) {
String error_message = format("The number of samples (src) must equal the number of labels (labels)! len(src)=%d, len(labels)=%d.", N, labels.total());
CV_Error(Error::StsBadArg, error_message);
} else if(labels.rows != 1 && labels.cols != 1) {
String error_message = format("Expected the labels in a matrix with one row or column! Given dimensions are rows=%s, cols=%d.", labels.rows, labels.cols);
CV_Error(Error::StsBadArg, error_message);
}
// clear existing model data
_labels.release();
_projections.clear();
// safely copy from cv::Mat to std::vector
std::vector<int> ll;
for(unsigned int i = 0; i < labels.total(); i++) {
ll.push_back(labels.at<int>(i));
}
// get the number of unique classes
int C = (int) remove_dups(ll).size();
// clip number of components to be a valid number
if((_num_components <= 0) || (_num_components > (C-1)))
_num_components = (C-1);
// perform a PCA and keep (N-C) components
PCA pca(data, Mat(), PCA::DATA_AS_ROW, (N-C));
// project the data and perform a LDA on it
LDA lda(pca.project(data),labels, _num_components);
// store the total mean vector
_mean = pca.mean.reshape(1,1);
// store labels
_labels = labels.clone();
// store the eigenvalues of the discriminants
lda.eigenvalues().convertTo(_eigenvalues, CV_64FC1);
// Now calculate the projection matrix as pca.eigenvectors * lda.eigenvectors.
// Note: OpenCV stores the eigenvectors by row, so we need to transpose it!
gemm(pca.eigenvectors, lda.eigenvectors(), 1.0, Mat(), 0.0, _eigenvectors, GEMM_1_T);
// store the projections of the original data
for(int sampleIdx = 0; sampleIdx < data.rows; sampleIdx++) {
Mat p = LDA::subspaceProject(_eigenvectors, _mean, data.row(sampleIdx));
_projections.push_back(p);
}
}
Matrix operator * (const Matrix& A, const Matrix& B)
{
if (A.Clo() != B.Rlo() || A.Chi() != B.Rhi())
Matpack.Error("Matrix operator * (const Matrix&, const Matrix&): "
"non conformant arguments\n");
// allocate return matrix
Matrix C(A.Rlo(),A.Rhi(),B.Clo(),B.Chi());
//------------------------------------------------------------------------//
// the BLAS version
//------------------------------------------------------------------------//
#if defined ( _MATPACK_USE_BLAS_ )
if ( LT(B) ) { // full matrix * lower triangle
#ifdef DEBUG
cout << "GM*LT\n";
#endif
checksquare(B);
// copy A to C to protect from overwriting
copyvec(C.Store(),A.Store(),A.Elements());
charT side('L'), uplo('U'), transc('N'), diag('N');
intT m(C.Cols()), n(C.Rows()),
ldb(B.Cols()), ldc(C.Cols());
doubleT alpha(1.0);
F77NAME(dtrmm)(&side,&uplo,&transc,&diag,&m,&n,
&alpha,B.Store(),&ldb, C.Store(),&ldc);
} else if ( UT(B) ) { // full matrix * upper triangle
#ifdef DEBUG
cout << "GM*UT\n";
#endif
checksquare(B);
// copy A to C to protect from overwriting
copyvec(C.Store(),A.Store(),A.Elements());
charT side('L'), uplo('L'), transc('N'), diag('N');
intT m(C.Cols()), n(C.Rows()),
ldb(B.Cols()), ldc(C.Cols());
doubleT alpha(1.0);
F77NAME(dtrmm)(&side,&uplo,&transc,&diag,&m,&n,
&alpha,B.Store(),&ldb, C.Store(),&ldc);
} else if ( LT(A) ) { // lower triangle * full matrix
#ifdef DEBUG
cout << "LT*GM\n";
#endif
checksquare(A);
// copy B to C to protect from overwriting
copyvec(C.Store(),B.Store(),B.Elements());
charT side('R'), uplo('U'), transc('N'), diag('N');
intT m(C.Cols()), n(C.Rows()),
ldb(A.Cols()), ldc(C.Cols());
doubleT alpha(1.0);
F77NAME(dtrmm)(&side,&uplo,&transc,&diag,&m,&n,
&alpha,A.Store(),&ldb, C.Store(),&ldc);
} else if ( UT(A) ) { // upper triangle * full matrix
#ifdef DEBUG
cout << "UT*GM\n";
#endif
checksquare(A);
// copy A to C to protect from overwriting
copyvec(C.Store(),B.Store(),B.Elements());
charT side('R'), uplo('L'), transc('N'), diag('N');
intT m(C.Cols()), n(C.Rows()),
ldb(A.Cols()), ldc(C.Cols());
doubleT alpha(1.0);
F77NAME(dtrmm)(&side,&uplo,&transc,&diag,&m,&n,
&alpha,A.Store(),&ldb, C.Store(),&ldc);
} else /* GM(A) and GM(B) */ { // GM*GM: full matrix * full matrix
#ifdef DEBUG
cout << "GM*GM\n";
#endif
charT t('N');
intT m(B.Cols()), n(A.Rows()), k(B.Rows()),
lda(A.Cols()), ldb(B.Cols()), ldc(C.Cols());
doubleT alpha(1.0), beta(0.0);
F77NAME(dgemm)(&t,&t, &m,&n,&k,
&alpha,B.Store(),&ldb, A.Store(),&lda,
&beta,C.Store(),&ldc);
}
//------------------------------------------------------------------------//
// the non-BLAS version
//------------------------------------------------------------------------//
#else
int cl = A.cl, ch = A.ch,
arl = A.rl, arh = A.rh,
bcl = B.cl, bch = B.ch;
// avoid call to index operator that optimizes very badely
double **a = A.M, **b = B.M, **c = C.M;
for (int i = arl; i <= arh; i++) {
for (int j = bcl; j <= bch; j++) c[i][j] = 0.0;
for (int l = cl; l <= ch; l++) {
if ( a[i][l] != 0.0 ) {
double temp = a[i][l];
for (int j = bcl; j <= bch; j++)
c[i][j] += temp * b[l][j];
}
}
}
#endif
return C.Value();
}
/* http://codebase64.org/doku.php?id=base:small_fast_16-bit_prng */
unsigned short random16(void) {
path=0;
path|=PATH_R16;
lda(SEEDL); cycles+=3;
if (a==0) {
cycles+=3;
goto low_zero;
}
cycles+=2;
//lownz:
path|=PATH_LNZ;
asl_mem(SEEDL); cycles+=5;
lda(SEEDH); cycles+=3;
rol(); cycles+=2;
if (c==1) {
cycles+=3;
goto five_cycle_do_eor;
}
cycles+=2;
if (c==0) {
cycles+=3;
goto two_cycle_no_eor;
}
fprintf(stderr,"CAN'T HAPPEN\n");
eleven_cycle_do_eor:
cycles+=6;
five_cycle_do_eor:
cycles+=2;
three_cycle_do_eor:
sta(SEEDH); cycles+=3;
//do_eor:
path|=PATH_DEO;
a=a^0x76; cycles+=2;
sta(SEEDH); cycles+=3;
lda(SEEDL); cycles+=3;
a=a^0x57; cycles+=2;
sta(SEEDL); cycles+=3;
eor_rts:
cycles+=6;
return ((ram[SEEDH]<<8)|ram[SEEDL]);
six_cycles_no_eor:
cycles+=2;
four_cycle_no_eor:
cycles+=2;
two_cycle_no_eor:
cycles+=2;
//no_eor:
cycles+=2;
path|=PATH_NEO;
cycles+=6;
sta(SEEDH); cycles+=3;
cycles+=3;
goto eor_rts;
low_zero:
path|=PATH_LOZ;
lda(SEEDH); cycles+=3;
if (a==0) {
cycles+=3;
goto eleven_cycle_do_eor;
}
cycles+=2;
//ceo:
path|=PATH_CEO;
asl(); cycles+=2;
if (a==0) {
cycles+=3;
goto six_cycles_no_eor;
}
cycles+=2;
//cep:
path|=PATH_CEP;
if (c==0) {
cycles+=3;
goto four_cycle_no_eor;
}
cycles+=2;
if (c==1) {
cycles+=3;
goto three_cycle_do_eor;
}
cycles+=2;
return 0;
}
//! Fill all entries of the matrix with the given value.
void
fill (const Scalar value)
{
fill_matrix (nrows(), ncols(), get(), lda(), value);
}
//! A const view of the matrix.
const_mat_view_type const_view () const {
return const_mat_view_type (nrows(), ncols(),
const_cast<const Scalar*> (get()), lda());
}
static void hglin(void) {
// F53A
pha();
c=1;
sbc(ram[HGR_X]);
pha();
a=x;
sbc(ram[HGR_X+1]);
ram[HGR_QUADRANT]=a;
// F544
if (c==1) goto hglin_1;
pla();
a=a^0xff;
adc(1);
pha();
lda_const(0);
sbc(ram[HGR_QUADRANT]);
// F550
hglin_1:
ram[HGR_DX+1]=a;
ram[HGR_E+1]=a;
pla();
ram[HGR_DX]=a;
ram[HGR_E]=a;
pla();
ram[HGR_X]=a;
ram[HGR_X+1]=x;
a=y;
c=0;
sbc(ram[HGR_Y]);
if (c==0) goto hglin_2;
a=a^0xff;
adc(0xfe);
hglin_2:
// F568
ram[HGR_DY]=a;
ram[HGR_Y]=y;
ror_mem(HGR_QUADRANT);
c=1;
sbc(ram[HGR_DX]);
x=a;
lda_const(0xff);
sbc(ram[HGR_DX+1]);
ram[HGR_COUNT]=a;
ldy(HGR_HORIZ);
goto movex2; // always?
// f57c
movex:
asl();
move_left_or_right();
c=1;
// f581
movex2:
lda(HGR_E);
adc(ram[HGR_DY]);
ram[HGR_E]=a;
lda(HGR_E+1);
sbc(0);
movex2_1:
ram[HGR_E+1]=a;
lda(y_indirect(GBASL,y));
a=a^ram[HGR_BITS];
a=a&ram[HMASK];
a=a^ram[y_indirect(GBASL,y)];
ram[y_indirect(GBASL,y)]=a;
inx();
if (z!=1) goto movex2_2;
ram[HGR_COUNT]++;
if (ram[HGR_COUNT]==0) return;
// F59e
movex2_2:
lda(HGR_QUADRANT);
if (c==1) goto movex;
move_up_or_down();
c=0;
lda(HGR_E);
adc(ram[HGR_DX]);
ram[HGR_E]=a;
lda(HGR_E+1);
adc(ram[HGR_DX+1]);
goto movex2_1;
}
void run(double *accum, int *cur_loc, mem_array mem) {
int prg_counter = 0, // mem cell location of the command being executed
next_loc = 0, // mem cell location of the next command to be executed
run_flag = CONTINUE; // flag for when to stop the execution of the
// user's program. Values are CONTINUE, STOP
// and RUN_ERR
char cmdtrans[80]; // an English translation of the current command
enum speed run_speed; // the run mode
hidemouse();
// if they want to run
if(get_speed(&run_speed) == CONTINUE) {
// set up screen for running
put_accum(accum);
clear_monitor();
clear_keyboard();
clear_keys();
/* user's program loop */
do {
// execute at the next location
prg_counter = next_loc;
// THF patch, was +2
put_prg_counter(prg_counter + 1);
put_instruct(mem[prg_counter]);
bright_cell(prg_counter, mem[prg_counter]);
// case statement for run mode
switch(run_speed) {
case SLOW:
delay(SLOW_DELAY_TIME);
break;
case FAST:
delay(FAST_DELAY_TIME);
}
/// if there is a command in the cell
if(mem[prg_counter].entry_type == CMD) {
// command type case statement
switch(mem[prg_counter].cmd_type) {
case LDC:
run_flag = ldc(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case ADC:
run_flag = adc(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case LDA:
run_flag = lda(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case STA:
run_flag = sta(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case ADD:
run_flag = add(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case SUB:
run_flag = sub(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case MUL:
run_flag = mul(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case DIV:
run_flag = div(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case INP:
run_flag = inp(mem, cmdtrans, prg_counter, &next_loc);
break;
case OUT:
run_flag = out(mem, cmdtrans, prg_counter, &next_loc);
break;
case BPA:
run_flag = bpa(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case BNA:
run_flag = bna(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case BZA:
run_flag = bza(accum, mem, cmdtrans, prg_counter, &next_loc);
break;
case BRU:
run_flag = bru(mem, cmdtrans, prg_counter, &next_loc);
break;
case STP:
run_flag = stp(cmdtrans, prg_counter, &next_loc);
if(run_speed == CYCLE) {
display_cmdtrans(cmdtrans);
}
break;
default:
run_err_message("ERROR: Unkown command at this location.");
run_flag = RUN_ERR;
break;
}
} else {
run_err_message("ERROR: Unkown command at this location.");
run_flag = RUN_ERR;
}
// check to see if the user wants to stop
if(kbhit()) {
if(getch() == EscKey) {
run_flag = STOP;
}
}
if((run_speed == CYCLE) && (run_flag == CONTINUE)) {
run_flag = display_cmdtrans(cmdtrans);
}
dim_cell(prg_counter, mem[prg_counter]);
} while((run_flag == CONTINUE) && (mem[prg_counter].cmd_type != STP));
// clear the registers when program is done
clear_instruct();
clear_prg_counter();
}
showmouse();
if(run_flag == RUN_ERR) {
*cur_loc = prg_counter;
}
display_keys();
}
//! A non-const view of the matrix.
mat_view_type view () {
return mat_view_type (nrows(), ncols(), get(), lda());
}
