static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) { switch (n) { case S390_V0L_REGNUM ... S390_V15L_REGNUM: env->vregs[n][1].ll = ldtul_p(mem_buf + 8); return 8; case S390_V16_REGNUM ... S390_V31_REGNUM: env->vregs[n][0].ll = ldtul_p(mem_buf); env->vregs[n][1].ll = ldtul_p(mem_buf + 8); return 16; default: return 0; } }
static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) { switch (n) { case S390_FPC_REGNUM: env->fpc = ldl_p(mem_buf); return 4; case S390_F0_REGNUM ... S390_F15_REGNUM: get_freg(env, n - S390_F0_REGNUM)->ll = ldtul_p(mem_buf); return 8; default: return 0; } }
int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { PowerPCCPU *cpu = POWERPC_CPU(cs); CPUPPCState *env = &cpu->env; int r = ppc_gdb_register_len(n); if (!r) { return r; } if (msr_le) { /* If cpu is in LE mode, convert memory contents to LE. */ ppc_gdb_swap_register(mem_buf, n, r); } if (n < 32) { /* gprs */ env->gpr[n] = ldtul_p(mem_buf); } else if (n < 64) { /* fprs */ env->fpr[n-32] = ldfq_p(mem_buf); } else { switch (n) { case 64: env->nip = ldtul_p(mem_buf); break; case 65: ppc_store_msr(env, ldtul_p(mem_buf)); break; case 66: { uint32_t cr = ldl_p(mem_buf); int i; for (i = 0; i < 8; i++) { env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF; } break; } case 67: env->lr = ldtul_p(mem_buf); break; case 68: env->ctr = ldtul_p(mem_buf); break; case 69: env->xer = ldtul_p(mem_buf); break; case 70: /* fpscr */ store_fpscr(env, ldtul_p(mem_buf), 0xffffffff); break; } } return r; }
static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) { switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: env->cregs[n] = ldtul_p(mem_buf); if (tcg_enabled()) { tlb_flush(ENV_GET_CPU(env), 1); } cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; default: return 0; } }
static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) { switch (n) { case S390_VIRT_CKC_REGNUM: env->ckc = ldtul_p(mem_buf); cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; case S390_VIRT_CPUTM_REGNUM: env->cputm = ldtul_p(mem_buf); cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; case S390_VIRT_BEA_REGNUM: env->gbea = ldtul_p(mem_buf); cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; case S390_VIRT_PREFIX_REGNUM: env->psa = ldtul_p(mem_buf); cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; case S390_VIRT_PP_REGNUM: env->pp = ldtul_p(mem_buf); cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; case S390_VIRT_PFT_REGNUM: env->pfault_token = ldtul_p(mem_buf); cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; case S390_VIRT_PFS_REGNUM: env->pfault_select = ldtul_p(mem_buf); cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; case S390_VIRT_PFC_REGNUM: env->pfault_compare = ldtul_p(mem_buf); cpu_synchronize_post_init(ENV_GET_CPU(env)); return 8; default: return 0; } }
int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { S390CPU *cpu = S390_CPU(cs); CPUS390XState *env = &cpu->env; target_ulong tmpl = ldtul_p(mem_buf); switch (n) { case S390_PSWM_REGNUM: env->psw.mask = tmpl; if (tcg_enabled()) { env->cc_op = extract64(tmpl, 44, 2); } break; case S390_PSWA_REGNUM: env->psw.addr = tmpl; break; case S390_R0_REGNUM ... S390_R15_REGNUM: env->regs[n - S390_R0_REGNUM] = tmpl; break; default: return 0; } return 8; }
int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; uint32_t tmp; if (n < CPU_NB_REGS) { if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { env->regs[gpr_map[n]] = ldtul_p(mem_buf); return sizeof(target_ulong); } else if (n < CPU_NB_REGS32) { n = gpr_map32[n]; env->regs[n] &= ~0xffffffffUL; env->regs[n] |= (uint32_t)ldl_p(mem_buf); return 4; } } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { #ifdef USE_X86LDOUBLE /* FIXME: byteswap float values - after fixing fpregs layout. */ memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10); #endif return 10; } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { n -= IDX_XMM_REGS; if (n < CPU_NB_REGS32 || (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) { env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf); env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8); return 16; } } else { switch (n) { case IDX_IP_REG: if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) { env->eip = ldq_p(mem_buf); return 8; } else { env->eip &= ~0xffffffffUL; env->eip |= (uint32_t)ldl_p(mem_buf); return 4; } case IDX_FLAGS_REG: env->eflags = ldl_p(mem_buf); return 4; case IDX_SEG_REGS: return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf); case IDX_SEG_REGS + 1: return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf); case IDX_SEG_REGS + 2: return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf); case IDX_SEG_REGS + 3: return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf); case IDX_SEG_REGS + 4: return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf); case IDX_SEG_REGS + 5: return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf); case IDX_FP_REGS + 8: cpu_set_fpuc(env, ldl_p(mem_buf)); return 4; case IDX_FP_REGS + 9: tmp = ldl_p(mem_buf); env->fpstt = (tmp >> 11) & 7; env->fpus = tmp & ~0x3800; return 4; case IDX_FP_REGS + 10: /* ftag */ return 4; case IDX_FP_REGS + 11: /* fiseg */ return 4; case IDX_FP_REGS + 12: /* fioff */ return 4; case IDX_FP_REGS + 13: /* foseg */ return 4; case IDX_FP_REGS + 14: /* fooff */ return 4; case IDX_FP_REGS + 15: /* fop */ return 4; case IDX_MXCSR_REG: cpu_set_mxcsr(env, ldl_p(mem_buf)); return 4; } } /* Unrecognised register. */ return 0; }
int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; target_ulong tmp; tmp = ldtul_p(mem_buf); if (n < 32) { env->active_tc.gpr[n] = tmp; return sizeof(target_ulong); } if (env->CP0_Config1 & (1 << CP0C1_FP) && n >= 38 && n < 73) { if (n < 70) { if (env->CP0_Status & (1 << CP0St_FR)) { env->active_fpu.fpr[n - 38].d = tmp; } else { env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; } } switch (n) { case 70: env->active_fpu.fcr31 = tmp & 0xFF83FFFF; /* set rounding mode */ RESTORE_ROUNDING_MODE; break; case 71: env->active_fpu.fcr0 = tmp; break; } return sizeof(target_ulong); } switch (n) { case 32: env->CP0_Status = tmp; break; case 33: env->active_tc.LO[0] = tmp; break; case 34: env->active_tc.HI[0] = tmp; break; case 35: env->CP0_BadVAddr = tmp; break; case 36: env->CP0_Cause = tmp; break; case 37: env->active_tc.PC = tmp & ~(target_ulong)1; if (tmp & 1) { env->hflags |= MIPS_HFLAG_M16; } else { env->hflags &= ~(MIPS_HFLAG_M16); } break; case 72: /* fp, ignored */ break; default: if (n > 89) { return 0; } /* Other registers are readonly. Ignore writes. */ break; } return sizeof(target_ulong); }