void mlprintf_ff(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
ll_printf(PRINTF_MSG|PRINTF_LOG|PRINTF_FF, NULL, fmt, ap);
va_end(ap);
}
void mprintf(const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
ll_printf(PRINTF_MSG, NULL, fmt, ap);
va_end(ap);
}
void lfprintf(u4_t printf_type, const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
ll_printf(printf_type, NULL, fmt, ap);
va_end(ap);
}
void clprintf(conn_t *c, const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
ll_printf(PRINTF_LOG, c, fmt, ap);
va_end(ap);
}
void write_rld_cfg(rldram_csr_config_t *cfg_ptr)
{
cvmx_dfa_memcfg0_t memcfg0;
cvmx_dfa_memcfg2_t memcfg2;
memcfg0.u64 = cfg_ptr->dfa_memcfg0_base;
if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
{
uint32_t dfa_memcfg0;
if (OCTEON_IS_MODEL (OCTEON_CN58XX)) {
// Set RLDQK90_RST and RDLCK_RST to reset all three DLLs.
memcfg0.s.rldck_rst = 1;
memcfg0.s.rldqck90_rst = 1;
cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x clk/qk90 reset\n", (uint32_t) memcfg0.u64);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64);
// Clear RDLCK_RST while asserting RLDQK90_RST to bring RLDCK DLL out of reset.
memcfg0.s.rldck_rst = 0;
memcfg0.s.rldqck90_rst = 1;
cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64);
cvmx_wait(4000000); /* Wait */
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x qk90 reset\n", (uint32_t) memcfg0.u64);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64);
// Clear both RDLCK90_RST and RLDQK90_RST to bring the RLDQK90 DLL out of reset.
memcfg0.s.rldck_rst = 0;
memcfg0.s.rldqck90_rst = 0;
cvmx_write_csr(CVMX_DFA_MEMCFG0, memcfg0.u64);
cvmx_wait(4000000); /* Wait */
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x DLL out of reset\n", (uint32_t) memcfg0.u64);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), memcfg0.u64);
}
//=======================================================================
// Now print out the sequence of events:
cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x port enables\n", cfg_ptr->dfa_memcfg0_base);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base);
cvmx_wait(4000000); /* Wait */
cvmx_write_csr(CVMX_DFA_MEMCFG1, cfg_ptr->dfa_memcfg1_base);
ll_printf("CVMX_DFA_MEMCFG1: 0x%08x\n", cfg_ptr->dfa_memcfg1_base);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG1 & ~(1ull<<63), cfg_ptr->dfa_memcfg1_base);
if (cfg_ptr->p0_ena ==1)
{
cvmx_write_csr(CVMX_DFA_MEMRLD, cfg_ptr->mrs_dat_p0bunk0);
ll_printf("CVMX_DFA_MEMRLD : 0x%08x p0_ena memrld\n", cfg_ptr->mrs_dat_p0bunk0);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p0bunk0);
dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base |
(1 << 23) | // P0_INIT
(1 << 25) // BUNK_INIT[1:0]=Bunk#0
);
cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x p0_init/bunk_init\n", dfa_memcfg0);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
cvmx_wait(RLD_INIT_DELAY);
ll_printf("Delay.....\n");
cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x back to base\n", cfg_ptr->dfa_memcfg0_base);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base);
}
if (cfg_ptr->p1_ena ==1)
{
cvmx_write_csr(CVMX_DFA_MEMRLD, cfg_ptr->mrs_dat_p1bunk0);
ll_printf("CVMX_DFA_MEMRLD : 0x%08x p1_ena memrld\n", cfg_ptr->mrs_dat_p1bunk0);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p1bunk0);
dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base |
(1 << 24) | // P1_INIT
(1 << 25) // BUNK_INIT[1:0]=Bunk#0
);
cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x p1_init/bunk_init\n", dfa_memcfg0);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
cvmx_wait(RLD_INIT_DELAY);
ll_printf("Delay.....\n");
cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x back to base\n", cfg_ptr->dfa_memcfg0_base);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base);
}
// P0 Bunk#1
if ((cfg_ptr->p0_ena ==1) && (cfg_ptr->bunkport == 2))
{
cvmx_write_csr(CVMX_DFA_MEMRLD, cfg_ptr->mrs_dat_p0bunk1);
ll_printf("CVMX_DFA_MEMRLD : 0x%08x p0_ena memrld\n", cfg_ptr->mrs_dat_p0bunk1);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p0bunk1);
dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base |
(1 << 23) | // P0_INIT
(2 << 25) // BUNK_INIT[1:0]=Bunk#1
);
cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x p0_init/bunk_init\n", dfa_memcfg0);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
cvmx_wait(RLD_INIT_DELAY);
ll_printf("Delay.....\n");
if (cfg_ptr->p1_ena == 1)
{ // Re-arm Px_INIT if P1-B1 init is required
cvmx_write_csr(CVMX_DFA_MEMCFG0, cfg_ptr->dfa_memcfg0_base);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x px_init rearm\n", cfg_ptr->dfa_memcfg0_base);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), cfg_ptr->dfa_memcfg0_base);
}
}
if ((cfg_ptr->p1_ena == 1) && (cfg_ptr->bunkport == 2))
{
cvmx_write_csr(CVMX_DFA_MEMRLD, cfg_ptr->mrs_dat_p1bunk1);
ll_printf("CVMX_DFA_MEMRLD : 0x%08x p1_ena memrld\n", cfg_ptr->mrs_dat_p1bunk1);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMRLD & ~(1ull<<63), cfg_ptr->mrs_dat_p1bunk1);
dfa_memcfg0 = ( cfg_ptr->dfa_memcfg0_base |
(1 << 24) | // P1_INIT
(2 << 25) // BUNK_INIT[1:0]=10
);
cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x p1_init/bunk_init\n", dfa_memcfg0);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
}
cvmx_wait(4000000); // 1/100S, 0.01S, 10mS
ll_printf("Delay.....\n");
/* Enable bunks */
dfa_memcfg0 = cfg_ptr->dfa_memcfg0_base |((cfg_ptr->bunkport >= 1) << 25) | ((cfg_ptr->bunkport == 2) << 26);
cvmx_write_csr(CVMX_DFA_MEMCFG0, dfa_memcfg0);
ll_printf("CVMX_DFA_MEMCFG0: 0x%08x enable bunks\n", dfa_memcfg0);
cvmx_csr_db_decode(cvmx_get_proc_id(), CVMX_DFA_MEMCFG0 & ~(1ull<<63), dfa_memcfg0);
cvmx_wait(RLD_INIT_DELAY);
ll_printf("Delay.....\n");
/* Issue a Silo reset by toggling SILRST in memcfg2. */
memcfg2.u64 = cvmx_read_csr (CVMX_DFA_MEMCFG2);
memcfg2.s.silrst = 1;
cvmx_write_csr (CVMX_DFA_MEMCFG2, memcfg2.u64);
ll_printf("CVMX_DFA_MEMCFG2: 0x%08x silo reset start\n", (uint32_t) memcfg2.u64);
memcfg2.s.silrst = 0;
cvmx_write_csr (CVMX_DFA_MEMCFG2, memcfg2.u64);
ll_printf("CVMX_DFA_MEMCFG2: 0x%08x silo reset done\n", (uint32_t) memcfg2.u64);
}
}
