int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision ();
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
/*
* Initialize local bus.
*/
local_bus_init ();
/*
* Hack TSEC 3 and 4 IO voltages.
*/
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
ecm->eedr = 0xffffffff; /* clear ecm errors */
ecm->eeer = 0xffffffff; /* enable ecm errors */
return 0;
}
int board_early_init_f (void)
{
/*
* Initialize local bus.
*/
local_bus_init ();
enable_8568mds_duart();
enable_8568mds_flash_write();
#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
reset_8568mds_uccs();
#endif
#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
enable_8568mds_qe_mdio();
#endif
#ifdef CONFIG_SYS_I2C2_OFFSET
/* Enable I2C2_SCL and I2C2_SDA */
volatile struct par_io *port_c;
port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
port_c->cpdir2 |= 0x0f000000;
port_c->cppar2 &= ~0x0f000000;
port_c->cppar2 |= 0x0a000000;
#endif
return 0;
}
int board_early_init_f (void)
{
/*
* Initialize local bus.
*/
local_bus_init ();
enable_8569mds_flash_write();
#ifdef CONFIG_QE
enable_8569mds_qe_uec();
#endif
#if CONFIG_SYS_I2C2_OFFSET
/* Enable I2C2 signals instead of SD signals */
volatile struct ccsr_gur *gur;
gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
gur->plppar1 |= PLPPAR1_I2C2_VAL;
gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
gur->plpdir1 |= PLPDIR1_I2C2_VAL;
disable_8569mds_brd_eeprom_write_protect();
#endif
return 0;
}
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
char *src;
int f;
char *s = getenv("serial#");
puts("Board: Socrates");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef CONFIG_PCI
/* Check the PCI_clk sel bit */
if (in_be32(&gur->porpllsr) & (1<<15)) {
src = "SYSCLK";
f = CONFIG_SYS_CLK_FREQ;
} else {
src = "PCI_CLK";
f = CONFIG_PCI_CLK_FREQ;
}
printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
#else
printf ("PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int checkboard (void)
{
char *s = getenv("serial#");
printf("Board: %s", CONFIG_BOARDNAME);
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
#ifdef CONFIG_PCI
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
printf ("PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int checkboard(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
puts("Board: Mercury Computer Systems, Inc. MPQ-101 ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
putc('\n');
/*
* Initialize local bus.
*/
local_bus_init();
/*
* Hack TSEC 3 and 4 IO voltages.
*/
out_be32(&gur->tsec34ioovcr, 0xe7e0); /* 1110 0111 1110 0xxx */
out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
return 0;
}
int checkboard (void)
{
char *s = getenv ("serial#");
printf ("Board: %s", CONFIG_BOARDNAME);
if (s != NULL) {
puts (", serial# ");
puts (s);
}
putc ('\n');
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int checkboard (void)
{
puts("Board: ADS\n");
#ifdef CONFIG_PCI
printf("PCI1: 32 bit, %d MHz (compiled)\n",
CONFIG_SYS_CLK_FREQ / 1000000);
#else
printf("PCI1: disabled\n");
#endif
/*
* Initialize local bus.
*/
local_bus_init();
return 0;
}
int checkboard (void)
{
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
uint cpu_board_rev = get_cpu_board_revision ();
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
printf (" PCI1: %d bit, %s MHz, %s\n",
(pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :
(pci1_speed == 66000000) ? "66" : "unknown",
pci1_clk_sel ? "sync" : "async");
if (pci_dual) {
printf (" PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
printf (" PCI2: disabled\n");
}
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
char buf[32];
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
uint cpu_board_rev = get_cpu_board_revision ();
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
printf("PCI1: %d bit, %s MHz, %s\n",
(pci1_32) ? 32 : 64,
strmhz(buf, pci1_speed),
pci1_clk_sel ? "sync" : "async");
if (pci_dual) {
printf("PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
printf("PCI2: disabled\n");
}
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
int checkboard (void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
uint cpu_board_rev = get_cpu_board_revision ();
uint svr;
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
/*
* Initialize local bus.
*/
local_bus_init ();
svr = get_svr();
/*
* Fix CPU2 errata: A core hang possible while executing a
* msync instruction and a snoopable transaction from an I/O
* master tagged to make quick forward progress is present.
* Fixed in Silicon Rev.2.1
*/
if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1))
ecm->eebpcr |= (1 << 16);
/*
* Hack TSEC 3 and 4 IO voltages.
*/
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
ecm->eedr = 0xffffffff; /* clear ecm errors */
ecm->eeer = 0xffffffff; /* enable ecm errors */
return 0;
}
