TPacket TProcessingElement::trafficBitReversal()
{
int nbits = (int)log2ceil((double)(TGlobalParams::mesh_dim_x*TGlobalParams::mesh_dim_y));
int dnode = 0;
for (int i=0; i<nbits; i++)
setBit(dnode, i, getBit(local_id, nbits-i-1));
TPacket p;
p.src_id = local_id;
p.dst_id = dnode;
p.timestamp = sc_time_stamp().to_double()/1000;
p.size = p.flit_left = getRandomSize();
return p;
}
Packet ProcessingElement::trafficShuffle()
{
int nbits =
(int)
log2ceil((double)
(GlobalParams::mesh_dim_x *
GlobalParams::mesh_dim_y));
int dnode = 0;
for (int i = 0; i < nbits - 1; i++)
setBit(dnode, i + 1, getBit(local_id, i));
setBit(dnode, 0, getBit(local_id, nbits - 1));
Packet p;
p.src_id = local_id;
p.dst_id = dnode;
p.timestamp = sc_time_stamp().to_double() / GlobalParams::clock_period_ps;
p.size = p.flit_left = getRandomSize();
return p;
}
NoximPacket NoximProcessingElement::trafficBitReversal()
{
int nbits = (int)log2ceil(
(double)(NoximGlobalParams::mesh_dim_x *
NoximGlobalParams::mesh_dim_y *
NoximGlobalParams::mesh_dim_z ));
int dnode = 0;
for (int i = 0; i < nbits; i++)
setBit(dnode, i, getBit(local_id, nbits - i - 1));
NoximPacket p;
p.src_id = local_id;
p.dst_id = dnode;
p.timestamp = sc_time_stamp().to_double() / 1000;
p.size = p.flit_left = getRandomSize();
// if (p.src_id == p.dst_id)
// cout << "Traffic generator has generated a packet is sent from a node to itself !!! \n";
return p;
}
NoximPacket NoximProcessingElement::trafficButterfly()
{
int nbits =
(int)
log2ceil((double)
(NoximGlobalParams::mesh_dim_x *
NoximGlobalParams::mesh_dim_y));
int dnode = 0;
for (int i = 1; i < nbits - 1; i++)
setBit(dnode, i, getBit(local_id, i));
setBit(dnode, 0, getBit(local_id, nbits - 1));
setBit(dnode, nbits - 1, getBit(local_id, 0));
NoximPacket p;
p.src_id = local_id;
p.dst_id = dnode;
p.timestamp = sc_time_stamp().to_double() / 1000;
p.size = p.flit_left = getRandomSize();
return p;
}
errval_t pcie_setup_confspace(void) {
errval_t err;
uint64_t address;
uint16_t segment;
uint8_t sbus;
uint8_t ebus;
struct acpi_rpc_client* cl = get_acpi_rpc_client();
cl->vtbl.get_pcie_confspace(cl, &err, &address, &segment, &sbus, &ebus);
if (err_is_ok(err)) {
size_t region_pages = (ebus + 1 - sbus) << 8;
size_t region_bytes = region_pages * BASE_PAGE_SIZE;
uint8_t region_bits = log2ceil(region_bytes);
struct capref pcie_cap;
struct acpi_rpc_client* acl = get_acpi_rpc_client();
errval_t error_code;
err = acl->vtbl.mm_alloc_range_proxy(acl, region_bits, address,
address + (1UL << region_bits), &pcie_cap, &error_code);
if (err_is_fail(err)) {
return err;
}
if (err_is_fail(error_code)) {
return error_code;
}
PCI_DEBUG("calling confspace init with: %"PRIu64", %"PRIu16", %"PRIu8", %"PRIu8"",
address, segment, sbus, ebus);
int r = pcie_confspace_init(pcie_cap, address, segment, sbus, ebus);
assert(r == 0);
}
return err;
}
void TNoC::buildMesh()
{
// Check for routing table availability
if (TGlobalParams::routing_algorithm == ROUTING_TABLE_BASED)
assert(grtable.load(TGlobalParams::routing_table_filename));
// Check for traffic table availability
if (TGlobalParams::traffic_distribution == TRAFFIC_TABLE_BASED)
assert(gttable.load(TGlobalParams::traffic_table_filename));
// Create the mesh as a matrix of tiles
for (int i = 0; i < TGlobalParams::mesh_dim_x; i++)
{
for (int j = 0; j < TGlobalParams::mesh_dim_y; j++)
{
// Create the single Tile with a proper name
char tile_name[20];
sprintf(tile_name, "Tile[%02d][%02d]", i, j);
t[i][j] = new TTile(tile_name);
// Tell to the router its coordinates
t[i][j]->r->configure(j * TGlobalParams::mesh_dim_x + i,
TGlobalParams::stats_warm_up_time,
TGlobalParams::buffer_depth, grtable);
// Tell to the PE its coordinates
t[i][j]->pe->local_id = j * TGlobalParams::mesh_dim_x + i;
t[i][j]->pe->traffic_table = >table; // Needed to choose destination
t[i][j]->pe->never_transmit = (gttable.occurrencesAsSource(
t[i][j]->pe->local_id) == 0);
// Map clock and reset
t[i][j]->clock(clock);
t[i][j]->reset(reset);
// Map Rx signals
t[i][j]->req_rx[DIRECTION_NORTH](req_to_south[i][j]);
t[i][j]->flit_rx[DIRECTION_NORTH](flit_to_south[i][j]);
t[i][j]->ack_rx[DIRECTION_NORTH](ack_to_north[i][j]);
t[i][j]->req_rx[DIRECTION_EAST](req_to_west[i + 1][j]);
t[i][j]->flit_rx[DIRECTION_EAST](flit_to_west[i + 1][j]);
t[i][j]->ack_rx[DIRECTION_EAST](ack_to_east[i + 1][j]);
t[i][j]->req_rx[DIRECTION_SOUTH](req_to_north[i][j + 1]);
t[i][j]->flit_rx[DIRECTION_SOUTH](flit_to_north[i][j + 1]);
t[i][j]->ack_rx[DIRECTION_SOUTH](ack_to_south[i][j + 1]);
t[i][j]->req_rx[DIRECTION_WEST](req_to_east[i][j]);
t[i][j]->flit_rx[DIRECTION_WEST](flit_to_east[i][j]);
t[i][j]->ack_rx[DIRECTION_WEST](ack_to_west[i][j]);
// Map in Rt signals
t[i][j]->rt_in[DIRECTION_NORTH](rt_to_south[i][j]);
t[i][j]->rt_in[DIRECTION_EAST](rt_to_west[i + 1][j]);
t[i][j]->rt_in[DIRECTION_SOUTH](rt_to_north[i][j + 1]);
t[i][j]->rt_in[DIRECTION_WEST](rt_to_east[i][j]);
// Map Tx signals
t[i][j]->req_tx[DIRECTION_NORTH](req_to_north[i][j]);
t[i][j]->flit_tx[DIRECTION_NORTH](flit_to_north[i][j]);
t[i][j]->ack_tx[DIRECTION_NORTH](ack_to_south[i][j]);
t[i][j]->req_tx[DIRECTION_EAST](req_to_east[i + 1][j]);
t[i][j]->flit_tx[DIRECTION_EAST](flit_to_east[i + 1][j]);
t[i][j]->ack_tx[DIRECTION_EAST](ack_to_west[i + 1][j]);
t[i][j]->req_tx[DIRECTION_SOUTH](req_to_south[i][j + 1]);
t[i][j]->flit_tx[DIRECTION_SOUTH](flit_to_south[i][j + 1]);
t[i][j]->ack_tx[DIRECTION_SOUTH](ack_to_north[i][j + 1]);
t[i][j]->req_tx[DIRECTION_WEST](req_to_west[i][j]);
t[i][j]->flit_tx[DIRECTION_WEST](flit_to_west[i][j]);
t[i][j]->ack_tx[DIRECTION_WEST](ack_to_east[i][j]);
// Map out rt signals
t[i][j]->rt_out[DIRECTION_NORTH](rt_to_north[i][j]);
t[i][j]->rt_out[DIRECTION_EAST](rt_to_east[i + 1][j]);
t[i][j]->rt_out[DIRECTION_SOUTH](rt_to_south[i][j + 1]);
t[i][j]->rt_out[DIRECTION_WEST](rt_to_west[i][j]);
// Map buffer level signals (analogy with req_tx/rx port mapping)
t[i][j]->free_slots[DIRECTION_NORTH](free_slots_to_north[i][j]);
t[i][j]->free_slots[DIRECTION_EAST](free_slots_to_east[i + 1][j]);
t[i][j]->free_slots[DIRECTION_SOUTH](free_slots_to_south[i][j + 1]);
t[i][j]->free_slots[DIRECTION_WEST](free_slots_to_west[i][j]);
t[i][j]->free_slots_neighbor[DIRECTION_NORTH](
free_slots_to_south[i][j]);
t[i][j]->free_slots_neighbor[DIRECTION_EAST](free_slots_to_west[i
+ 1][j]);
t[i][j]->free_slots_neighbor[DIRECTION_SOUTH](
free_slots_to_north[i][j + 1]);
t[i][j]->free_slots_neighbor[DIRECTION_WEST](
free_slots_to_east[i][j]);
// NoP
t[i][j]->NoP_data_out[DIRECTION_NORTH](NoP_data_to_north[i][j]);
t[i][j]->NoP_data_out[DIRECTION_EAST](NoP_data_to_east[i + 1][j]);
t[i][j]->NoP_data_out[DIRECTION_SOUTH](NoP_data_to_south[i][j + 1]);
t[i][j]->NoP_data_out[DIRECTION_WEST](NoP_data_to_west[i][j]);
t[i][j]->NoP_data_in[DIRECTION_NORTH](NoP_data_to_south[i][j]);
t[i][j]->NoP_data_in[DIRECTION_EAST](NoP_data_to_west[i + 1][j]);
t[i][j]->NoP_data_in[DIRECTION_SOUTH](NoP_data_to_north[i][j + 1]);
t[i][j]->NoP_data_in[DIRECTION_WEST](NoP_data_to_east[i][j]);
if(i == MASTER_X && j == MASTER_Y)
{
t[i][j]->pe->rtMaster = new RTMaster();
}
}
}
// dummy TNoP_data structure
TNoP_data tmp_NoP;
tmp_NoP.sender_id = NOT_VALID;
for (int i = 0; i < DIRECTIONS; i++)
{
tmp_NoP.channel_status_neighbor[i].free_slots = NOT_VALID;
tmp_NoP.channel_status_neighbor[i].available = false;
}
// Clear signals for borderline nodes
for (int i = 0; i <= TGlobalParams::mesh_dim_x; i++)
{
req_to_south[i][0] = 0;
ack_to_north[i][0] = 0;
req_to_north[i][TGlobalParams::mesh_dim_y] = 0;
ack_to_south[i][TGlobalParams::mesh_dim_y] = 0;
rt_to_south[i][0] = 0;
rt_to_north[i][TGlobalParams::mesh_dim_y] = 0;
free_slots_to_south[i][0].write(NOT_VALID);
free_slots_to_north[i][TGlobalParams::mesh_dim_y].write(NOT_VALID);
NoP_data_to_south[i][0].write(tmp_NoP);
NoP_data_to_north[i][TGlobalParams::mesh_dim_y].write(tmp_NoP);
}
for (int j = 0; j <= TGlobalParams::mesh_dim_y; j++)
{
req_to_east[0][j] = 0;
ack_to_west[0][j] = 0;
req_to_west[TGlobalParams::mesh_dim_x][j] = 0;
ack_to_east[TGlobalParams::mesh_dim_x][j] = 0;
rt_to_east[0][j] = 0;
rt_to_west[TGlobalParams::mesh_dim_x][j] = 0;
free_slots_to_east[0][j].write(NOT_VALID);
free_slots_to_west[TGlobalParams::mesh_dim_x][j].write(NOT_VALID);
NoP_data_to_east[0][j].write(tmp_NoP);
NoP_data_to_west[TGlobalParams::mesh_dim_x][j].write(tmp_NoP);
}
// invalidate reservation table entries for non-exhistent channels
for (int i = 0; i < TGlobalParams::mesh_dim_x; i++)
{
t[i][0]->r->reservation_table.invalidate(DIRECTION_NORTH);
t[i][TGlobalParams::mesh_dim_y - 1]->r->reservation_table.invalidate(
DIRECTION_SOUTH);
}
for (int j = 0; j < TGlobalParams::mesh_dim_y; j++)
{
t[0][j]->r->reservation_table.invalidate(DIRECTION_WEST);
t[TGlobalParams::mesh_dim_x - 1][j]->r->reservation_table.invalidate(
DIRECTION_EAST);
}
//int src[] = {10, 24, 12, 1, 9, 14, 5, 0, 11, 8, 19, 17, 4, 21, 3, 22, 18, 20, 6, 13, 23, 7, 15, 2, 16};
int src[] = {49, 38, 58, 46, 6, 39, 11, 2, 31, 23, 63, 44, 15, 48, 22, 36, 47, 41, 25, 26, 19, 20, 40, 16, 28, 62, 51, 18, 35, 10, 43, 53, 33, 57, 4, 61, 37, 21, 34, 32, 42, 50, 59, 24, 45, 12, 0, 60, 52, 1, 56, 29, 3, 14, 5, 17, 55, 30, 8, 54, 27, 9, 13, 7};
int i;
for(i = 0; i < sizeof(src)/sizeof(int); i++)
{
if(i >= TGlobalParams::num_flows)
break;
RTPath rtPath;
//insert a real-time path
rtPath.src = src[i];
//rtPath.dest = COORD2ID(TGlobalParams::mesh_dim_x - id2Coord(rtPath.src).y - 1, TGlobalParams::mesh_dim_y - id2Coord(rtPath.src).x - 1);
//butterfly
int nbits = (int) log2ceil((double) (TGlobalParams::mesh_dim_x
* TGlobalParams::mesh_dim_y));
int dnode = 0;
for (int k = 1; k < nbits - 1; k++)
setBit(dnode, k, getBit(rtPath.src, k));
setBit(dnode, 0, getBit(rtPath.src, nbits - 1));
setBit(dnode, nbits - 1, getBit(rtPath.src, 0));
rtPath.dest = dnode;
assert(dnode < TGlobalParams::mesh_dim_x * TGlobalParams::mesh_dim_y);
if(rtPath.src == rtPath.dest)
continue;
rtPath.sequence_no = 0;
rtPath.maxPacketLength = TGlobalParams::max_packet_size;
rtPath.minInterval = (int)(1 / TGlobalParams::packet_injection_rate);
rtPath.flowId = (rtPath.src * TGlobalParams::mesh_dim_x * TGlobalParams::mesh_dim_y + rtPath.dest) * 4;
t[id2Coord(rtPath.src).x][id2Coord(rtPath.src).y]->pe->rtPaths.push_back(rtPath);
}
cout << " Setting up " << i << " flows in the network" << endl;
}
