UINT16 m68307_sim::read_pbdat(address_space &space, UINT16 mem_mask) { int pc = space.device().safe_pc(); m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device()); if (m68k->m_m68307_portb_r) { // for general purpose bits, if configured as 'output' then anything output gets latched // and anything configured as input is read from the port UINT16 outputbits = m_pbddr; UINT16 inputbits = ~m_pbddr; UINT16 general_purpose_bits = ~m_pbcnt; UINT16 indat = m68k->m_m68307_portb_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines indat |= m68k->m_m68307_portb_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines UINT16 outdat = (m_pbdat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data) return (indat | outdat); } else { logerror("%08x m68307_internal_sim_r (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, mem_mask); } return 0xffff; }
static TIMER_CALLBACK( m68307_timer1_callback ) { legacy_cpu_device *dev = (legacy_cpu_device *)ptr; m68ki_cpu_core* m68k = m68k_get_safe_token(dev); m68307_single_timer* tptr = &m68k->m68307TIMER->singletimer[1]; tptr->regs[m68307TIMER_TMR] |= 0x2; m68307_timer1_interrupt(dev); tptr->mametimer->adjust(m68k->device->cycles_to_attotime(20000)); }
void m68307_timer::write_tmr(UINT16 data, UINT16 mem_mask, int which) { m68ki_cpu_core* m68k = m68k_get_safe_token(parent); m68307_single_timer* tptr = &singletimer[which]; COMBINE_DATA(&tptr->regs[m68307TIMER_TMR]); data = tptr->regs[m68307TIMER_TMR]; int ps = data & (0xff00)>>8; int ce = data & (0x00c0)>>6; int om = data & (0x0020)>>5; int ori = data & (0x0010)>>4; int frr = data & (0x0008)>>3; int iclk = data & (0x0006)>>1; int rst = data & (0x0001)>>0; logerror("tmr value %04x : Details :\n", data); logerror("prescale %d\n", ps); logerror("(clock divided by %d)\n", ps+1); logerror("capture edge / enable interrupt %d\n", ce); if (ce==0x0) logerror("(disable interrupt on capture event)\n"); if (ce==0x1) logerror("(capture on rising edge only + enable capture interrupt)\n"); if (ce==0x2) logerror("(capture on falling edge only + enable capture interrupt)\n"); if (ce==0x3) logerror("(capture on any edge + enable capture interrupt)\n"); logerror("output mode %d\n", om); if (om==0x0) logerror("(active-low pulse for one cycle))\n"); if (om==0x1) logerror("(toggle output)\n"); logerror("output reference interrupt %d\n", ori); if (ori==0x0) logerror("(disable reference interrupt)\n"); if (ori==0x1) logerror("(enable interrupt on reaching reference value))\n"); logerror("free running %d\n", frr); if (frr==0x0) logerror("(free running mode, counter continues after value reached)\n"); if (frr==0x1) logerror("(restart mode, counter resets after value reached)\n"); logerror("interrupt clock source %d\n", iclk); if (iclk==0x0) logerror("(stop count)\n"); if (iclk==0x1) logerror("(master system clock)\n"); if (iclk==0x2) logerror("(master system clock divided by 16)\n"); if (iclk==0x3) logerror("(TIN Pin)\n"); logerror("reset %d\n", rst); if (rst==0x0) logerror("(timer is reset)\n"); if (rst==0x1) logerror("(timer is running)\n"); tptr->mametimer->adjust(m68k->device->cycles_to_attotime(100000)); logerror("\n"); }
void m68307_sim::write_pbdat(address_space &space, UINT16 data, UINT16 mem_mask) { int pc = space.device().safe_pc(); m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device()); COMBINE_DATA(&m_pbdat); if (m68k->m_m68307_portb_w) { m68k->m_m68307_portb_w(space, false, data, mem_mask); } else { logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, data,mem_mask); } }
default: logerror("%08x m68340_internal_sim_r %04x (ILLEGAL?)\n", pc, offset); return space->machine().rand(); } } return 0x00; } READ32_HANDLER( m68340_internal_sim_cs_r ) { offset += m68340SIM_AM_CS0>>2; m68ki_cpu_core *m68k = m68k_get_safe_token(&space->device()); m68340_sim* sim = m68k->m68340SIM; assert(sim != NULL); if (sim) { int pc = cpu_get_pc(&space->device()); switch (offset<<2) { case m68340SIM_AM_CS0: return sim->m_am[0]; case m68340SIM_BA_CS0: return sim->m_ba[0]; case m68340SIM_AM_CS1: return sim->m_am[1]; case m68340SIM_BA_CS1: return sim->m_ba[1]; case m68340SIM_AM_CS2: return sim->m_am[2]; case m68340SIM_BA_CS2: return sim->m_ba[2];