static void s3c2410_pm_prepare(void) { /* ensure at least GSTATUS3 has the resume address */ __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); if (machine_is_h1940()) { void *base = phys_to_virt(H1940_SUSPEND_CHECK); unsigned long ptr; unsigned long calc = 0; /* generate check for the bootloader to check on resume */ for (ptr = 0; ptr < 0x40000; ptr += 0x400) calc += __raw_readl(base+ptr); __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); } /* RX3715 and RX1950 use similar to H1940 code and the * same offsets for resume and checksum pointers */ if (machine_is_rx3715() || machine_is_rx1950()) { void *base = phys_to_virt(H1940_SUSPEND_CHECK); unsigned long ptr; unsigned long calc = 0; /* generate check for the bootloader to check on resume */ for (ptr = 0; ptr < 0x40000; ptr += 0x4) calc += __raw_readl(base+ptr); __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); } if ( machine_is_aml_m5900() ) s3c2410_gpio_setpin(S3C2410_GPF(2), 1); if (machine_is_rx1950()) { /* According to S3C2442 user's manual, page 7-17, * when the system is operating in NAND boot mode, * the hardware pin configuration - EINT[23:21] – * must be set as input for starting up after * wakeup from sleep mode */ s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT); s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT); s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT); } }
static void s3c2410_pm_prepare(void) { /* ensure at least GSTATUS3 has the resume address */ { volatile unsigned long *ptr = phys_to_virt(0x30000900); *ptr = 0x55; } __raw_writel(0x7, S3C2410_GSTATUS2); S3C_PMDBG("GSTATUS2 0x%08x\n", __raw_readl(S3C2410_GSTATUS2)); __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); if (machine_is_h1940()) { void *base = phys_to_virt(H1940_SUSPEND_CHECK); unsigned long ptr; unsigned long calc = 0; /* generate check for the bootloader to check on resume */ for (ptr = 0; ptr < 0x40000; ptr += 0x400) calc += __raw_readl(base+ptr); __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); } /* the RX3715 uses similar code and the same H1940 and the * same offsets for resume and checksum pointers */ if (machine_is_rx3715()) { void *base = phys_to_virt(H1940_SUSPEND_CHECK); unsigned long ptr; unsigned long calc = 0; /* generate check for the bootloader to check on resume */ for (ptr = 0; ptr < 0x40000; ptr += 0x4) calc += __raw_readl(base+ptr); __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); } if ( machine_is_aml_m5900() ) s3c2410_gpio_setpin(S3C2410_GPF(2), 1); }
static void s3c2410_pm_resume(void) { unsigned long tmp; /* unset the return-from-sleep flag, to ensure reset */ tmp = __raw_readl(S3C2410_GSTATUS2); tmp &= S3C2410_GSTATUS2_OFFRESET; __raw_writel(tmp, S3C2410_GSTATUS2); if ( machine_is_aml_m5900() ) s3c2410_gpio_setpin(S3C2410_GPF(2), 0); }
static __init int pm_simtec_init(void) { unsigned long gstatus4; /* check which machine we are running on */ if (!machine_is_bast() && !machine_is_vr1000() && !machine_is_anubis() && !machine_is_osiris() && !machine_is_aml_m5900()) return 0; printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n"); gstatus4 = (__raw_readl(S3C2410_BANKCON7) & 0x3) << 30; gstatus4 |= (__raw_readl(S3C2410_BANKCON6) & 0x3) << 28; gstatus4 |= (__raw_readl(S3C2410_BANKSIZE) & S3C2410_BANKSIZE_MASK); __raw_writel(gstatus4, S3C2410_GSTATUS4); return s3c_pm_init(); }