/*
* USB Host1 HS port
*/
static int gpio_usbh1_active(void)
{
/* Set USBH1_STP to GPIO and toggle it */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO |
IOMUX_CONFIG_SION);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), "usbh1_stp");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP), 1);
/* Signal only used on MX51-3DS for reset to PHY.*/
if (machine_is_mx51_3ds()) {
mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH |
PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), "eim_d17");
gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 0);
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 1);
}
msleep(100);
return 0;
}
/*
* USB Host1 HS port
*/
static int gpio_usbh1_active(void)
{
iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D17__GPIO2_1;
int ret;
/* Set USBH1_STP to GPIO and toggle it */
mxc_iomux_v3_setup_pad(usbh1stp_gpio);
ret = gpio_request(MX5X_USBH1_STP, "usbh1_stp");
if (ret) {
pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
return ret;
}
gpio_direction_output(MX5X_USBH1_STP, 0);
gpio_set_value(MX5X_USBH1_STP, 1);
/* Signal only used on MX51-3DS for reset to PHY.*/
if (machine_is_mx51_3ds()) {
mxc_iomux_v3_setup_pad(phyreset_gpio);
ret = gpio_request(MX51_3DS_PHY_RESET, "eim_d17");
if (ret) {
pr_debug("failed to get MX51_PAD_EIM_D17__GPIO2_1: %d\n", ret);
return ret;
}
gpio_direction_output(MX51_3DS_PHY_RESET, 0);
gpio_set_value(MX51_3DS_PHY_RESET, 1);
}
msleep(100);
return 0;
}
static void gpio_usbh1_inactive(void)
{
/* Signal only used on MX51-3DS for reset to PHY.*/
if (machine_is_mx51_3ds()) {
gpio_free(MX51_3DS_PHY_RESET);
}
gpio_free(MX5X_USBH1_STP);
}
static void gpio_usbh1_inactive(void)
{
/* Signal only used on MX51-3DS for reset to PHY.*/
if (machine_is_mx51_3ds()) {
gpio_free(IOMUX_TO_GPIO(MX51_PIN_EIM_D17));
mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_GPIO);
}
mxc_free_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_GPIO);
gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP));
}
static int __init usbh2_init(void)
{
pr_debug("%s: \n", __func__);
if (machine_is_mx51_3ds() ||
(machine_is_mx51_babbage() && (cpu_is_mx51_rev(CHIP_REV_2_0) >= 1)))
return 0;
host_pdev_register(usbh2_resources, ARRAY_SIZE(usbh2_resources),
&usbh2_config);
return 0;
}
int mc13892_init_registers(void)
{
CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF));
CHECK_ERROR(pmic_write(REG_INT_MASK0, 0xFFFFFF));
CHECK_ERROR(pmic_write(REG_INT_STATUS0, 0xFFFFFF));
CHECK_ERROR(pmic_write(REG_INT_STATUS1, 0xFFFFFF));
/* disable auto charge */
if (machine_is_mx51_3ds())
CHECK_ERROR(pmic_write(REG_CHARGE, 0xB40003));
pm_power_off = mc13892_power_off;
return PMIC_SUCCESS;
}
static void otg_set_utmi_xcvr(void)
{
u32 tmp;
/* Stop then Reset */
UOG_USBCMD &= ~UCMD_RUN_STOP;
while (UOG_USBCMD & UCMD_RUN_STOP)
;
UOG_USBCMD |= UCMD_RESET;
while ((UOG_USBCMD) & (UCMD_RESET))
;
if (cpu_is_mx53())
USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
if (cpu_is_mx51()) {
if (machine_is_mx51_3ds()) {
/* OTG Polarity of Overcurrent is Low active */
USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL;
/* Enable OTG Overcurrent Event */
USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS;
} else {
/* BBG is not using OC */
USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
}
} else if (cpu_is_mx25()) {
USBCTRL |= UCTRL_OCPOL;
USBCTRL &= ~UCTRL_PP;
} else if (cpu_is_mx50()) {
USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS;
} else {
/* USBOTG_PWR low active */
USBCTRL &= ~UCTRL_PP;
/* OverCurrent Polarity is Low Active */
USBCTRL &= ~UCTRL_OCPOL;
if (cpu_is_mx35() && (imx_cpu_ver() < IMX_CHIP_REVISION_2_0))
/* OTG Lock Disable */
USBCTRL |= UCTRL_OLOCKD;
}
if (cpu_is_mx51())
USBCTRL &= ~UCTRL_OPM; /* OTG Power Mask */
USBCTRL &= ~UCTRL_OWIE; /* OTG Wakeup Intr Disable */
/* set UTMI xcvr */
tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK;
tmp |= PORTSC_PTS_UTMI;
UOG_PORTSC1 = tmp;
if (cpu_is_mx51()) {
/* Set the PHY clock to 19.2MHz */
USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK;
USB_PHY_CTR_FUNC2 |= 0x01;
}
/* Workaround an IC issue for ehci driver:
* when turn off root hub port power, EHCI set
* PORTSC reserved bits to be 0, but PTW with 0
* means 8 bits tranceiver width, here change
* it back to be 16 bits and do PHY diable and
* then enable.
*/
UOG_PORTSC1 |= PORTSC_PTW;
if (cpu_is_mx35() || cpu_is_mx25()) {
/* Enable UTMI interface in PHY control Reg */
USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE;
USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE;
}
/* need to reset the controller here so that the ID pin
* is correctly detected.
*/
/* Stop then Reset */
UOG_USBCMD &= ~UCMD_RUN_STOP;
while (UOG_USBCMD & UCMD_RUN_STOP)
;
UOG_USBCMD |= UCMD_RESET;
while ((UOG_USBCMD) & (UCMD_RESET))
;
/* allow controller to reset, and leave time for
* the ULPI transceiver to reset too.
*/
msleep(100);
if (cpu_is_mx37()) {
/* fix USB PHY Power Gating leakage issue for i.MX37 */
USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETON;
USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETEN;
}
/* Turn off the usbpll for UTMI tranceivers */
clk_disable(usb_clk);
}
