void baytrail_init_pre_device(void) { struct soc_gpio_config *config; fill_in_pattrs(); /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); /* Indicate S3 resume to rest of ramstage. */ s3_resume_prepare(); /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); }
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) { struct soc_gpio_config *gpio_config; fill_in_pattrs(); if (!config->disable_ddr_2x_refresh_rate) baytrail_enable_2x_refresh_rate(); /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); /* Indicate S3 resume to rest of ramstage. */ s3_resume_prepare(); /* Run reference code. */ baytrail_run_reference_code(); /* Get GPIO initial states from mainboard */ gpio_config = mainboard_get_gpios(); setup_soc_gpios(gpio_config, config->enable_xdp_tap); baytrail_init_scc(); }