/* ARGSUSED */
static void
mvusb_attach(device_t parent, device_t self, void *aux)
{
struct mvusb_softc *sc = device_private(self);
struct marvell_attach_args *mva = aux;
usbd_status r;
aprint_normal(": Marvell USB 2.0 Interface\n");
aprint_naive("\n");
sc->sc.sc_dev = self;
sc->sc.sc_bus.hci_private = sc;
sc->sc_model = mva->mva_model;
sc->sc_rev = mva->mva_revision;
sc->sc_iot = mva->mva_iot;
/* Map I/O registers for marvell usb */
if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
mva->mva_size, &sc->sc_ioh)) {
aprint_error_dev(self, "can't map registers\n");
return;
}
mvusb_init(sc, mva->mva_tags);
/* Map I/O registers for ehci */
sc->sc.sc_size = MARVELL_USB_EHCI_SIZE;
if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, MARVELL_USB_EHCI_BASE,
sc->sc.sc_size, &sc->sc.ioh)) {
aprint_error_dev(self, "can't subregion registers\n");
return;
}
sc->sc.iot = sc->sc_iot;
sc->sc.sc_bus.dmatag = mva->mva_dmat;
/* Disable interrupts, so we don't get any spurious ones. */
sc->sc.sc_offs = EREAD1(&sc->sc, EHCI_CAPLENGTH);
DPRINTF(("%s: offs=%d\n", device_xname(self), sc->sc.sc_offs));
EOWRITE2(&sc->sc, EHCI_USBINTR, 0);
marvell_intr_establish(mva->mva_irq, IPL_USB, ehci_intr, sc);
sc->sc.sc_bus.usbrev = USBREV_2_0;
/* Figure out vendor for root hub descriptor. */
sc->sc.sc_id_vendor = 0x0000; /* XXXXX */
strcpy(sc->sc.sc_vendor, "Marvell");
sc->sc.sc_vendor_init = mvusb_vendor_init;
sc->sc.sc_vendor_port_status = mvusb_vendor_port_status;
r = ehci_init(&sc->sc);
if (r != USBD_NORMAL_COMPLETION) {
aprint_error_dev(self, "init failed, error=%d\n", r);
return;
}
/* Attach usb device. */
sc->sc.sc_child = config_found(self, &sc->sc.sc_bus, usbctlprint);
}
/*
* cpu_initclocks:
*
* Initialize the clock and get them going.
*/
void
cpu_initclocks(void)
{
struct mvsoctmr_softc *sc;
void *clock_ih;
const int en = 1, autoen = 1;
uint32_t timer0_tval;
sc = mvsoctmr_sc;
if (sc == NULL)
panic("cpu_initclocks: mvsoctmr not found");
mvsoctmr_timecounter.tc_priv = sc;
if (sc->sc_flags & TMR_FLAGS_ARMADAXP)
/* We set global timer and counter to 25 MHz mode */
mvsoctmr_timecounter.tc_frequency = 25000000;
else
mvsoctmr_timecounter.tc_frequency = mvTclk;
timer0_tval = (mvsoctmr_timecounter.tc_frequency * 2) / (u_long) hz;
timer0_tval = (timer0_tval / 2) + (timer0_tval & 1);
mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, timer0_tval, en, autoen);
mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, 0xffffffff, en, autoen);
if (sc->sc_flags & TMR_FLAGS_ARMADAXP) {
/*
* Establishing timer interrupts is slightly different for
* Armada XP than for other supported SoCs from Marvell.
* Timer interrupt is no different from any other interrupt
* in Armada XP, so we use generic marvell_intr_establish().
*/
clock_ih = marvell_intr_establish(sc->sc_irq, IPL_CLOCK,
clockhandler, NULL);
} else
clock_ih = mvsoc_bridge_intr_establish(
MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ, IPL_CLOCK, clockhandler,
NULL);
if (clock_ih == NULL)
panic("cpu_initclocks: unable to register timer interrupt");
tc_init(&mvsoctmr_timecounter);
}
/* ARGSUSED */
static void
gttwsi_attach(device_t parent, device_t self, void *args)
{
struct marvell_attach_args *mva = args;
bus_space_handle_t ioh;
if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
mva->mva_size, &ioh)) {
aprint_error(": cannot map registers\n");
return;
}
gttwsi_attach_subr(self, mva->mva_iot, ioh);
marvell_intr_establish(mva->mva_irq, IPL_BIO, gttwsi_intr,
device_private(self));
gttwsi_config_children(self);
}
/* ARGSUSED */
static void
mvsatahc_attach(device_t parent, device_t self, void *aux)
{
struct mvsata_softc *sc = device_private(self);
struct marvell_attach_args *mva = aux;
uint32_t mask;
int port, i;
aprint_normal(": Marvell Serial-ATA Host Controller (SATAHC)\n");
aprint_naive("\n");
sc->sc_wdcdev.sc_atac.atac_dev = self;
sc->sc_model = mva->mva_model;
sc->sc_iot = mva->mva_iot;
if (bus_space_subregion(mva->mva_iot, mva->mva_ioh, mva->mva_offset,
mva->mva_size, &sc->sc_ioh)) {
aprint_error_dev(self, "can't map registers\n");
return;
}
sc->sc_dmat = mva->mva_dmat;
sc->sc_enable_intr = mvsatahc_enable_intr;
mvsatahc_wininit(sc, mva->mva_tags);
for (i = 0; i < __arraycount(mvsata_products); i++)
if (mva->mva_model == mvsata_products[i].model)
break;
KASSERT(i < __arraycount(mvsata_products));
if (mvsata_attach(sc, &mvsata_products[i], NULL, NULL, 0) != 0)
return;
marvell_intr_establish(mva->mva_irq, IPL_BIO, mvsatahc_intr, sc);
mask = 0;
for (port = 0; port < sc->sc_port; port++)
mask |=
MVSATAHC_MI_SATAERR(port) |
MVSATAHC_MI_SATADONE(port);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSATAHC_MIMR, mask);
}
