static void max310x_handle_tx(struct uart_port *port)
{
struct circ_buf *xmit = &port->state->xmit;
unsigned int txlen, to_send;
if (unlikely(port->x_char)) {
max310x_port_write(port, MAX310X_THR_REG, port->x_char);
port->icount.tx++;
port->x_char = 0;
return;
}
if (uart_circ_empty(xmit) || uart_tx_stopped(port))
return;
/* Get length of data pending in circular buffer */
to_send = uart_circ_chars_pending(xmit);
if (likely(to_send)) {
/* Limit to size of TX FIFO */
txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
txlen = port->fifosize - txlen;
to_send = (to_send > txlen) ? txlen : to_send;
/* Add data to send */
port->icount.tx += to_send;
while (to_send--) {
max310x_port_write(port, MAX310X_THR_REG,
xmit->buf[xmit->tail]);
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
}
}
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
}
static int max310x_startup(struct uart_port *port)
{
struct max310x_port *s = dev_get_drvdata(port->dev);
unsigned int val;
s->devtype->power(port, 1);
/* Configure MODE1 register */
max310x_port_update(port, MAX310X_MODE1_REG,
MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
/* Configure MODE2 register & Reset FIFOs*/
val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
max310x_port_write(port, MAX310X_MODE2_REG, val);
max310x_port_update(port, MAX310X_MODE2_REG,
MAX310X_MODE2_FIFORST_BIT, 0);
/* Configure flow control levels */
/* Flow control halt level 96, resume level 48 */
max310x_port_write(port, MAX310X_FLOWLVL_REG,
MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
/* Clear IRQ status register */
max310x_port_read(port, MAX310X_IRQSTS_REG);
/* Enable RX, TX, CTS change interrupts */
val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
return 0;
}
static int max310x_set_baud(struct uart_port *port, int baud)
{
unsigned int mode = 0, clk = port->uartclk, div = clk / baud;
/* Check for minimal value for divider */
if (div < 16)
div = 16;
if (clk % baud && (div / 16) < 0x8000) {
/* Mode x2 */
mode = MAX310X_BRGCFG_2XMODE_BIT;
clk = port->uartclk * 2;
div = clk / baud;
if (clk % baud && (div / 16) < 0x8000) {
/* Mode x4 */
mode = MAX310X_BRGCFG_4XMODE_BIT;
clk = port->uartclk * 4;
div = clk / baud;
}
}
max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8);
max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16);
max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode);
return DIV_ROUND_CLOSEST(clk, div);
}
static int max310x_rs485_config(struct uart_port *port,
struct serial_rs485 *rs485)
{
unsigned int val;
if (rs485->delay_rts_before_send > 0x0f ||
rs485->delay_rts_after_send > 0x0f)
return -ERANGE;
val = (rs485->delay_rts_before_send << 4) |
rs485->delay_rts_after_send;
max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
if (rs485->flags & SER_RS485_ENABLED) {
max310x_port_update(port, MAX310X_MODE1_REG,
MAX310X_MODE1_TRNSCVCTRL_BIT,
MAX310X_MODE1_TRNSCVCTRL_BIT);
max310x_port_update(port, MAX310X_MODE2_REG,
MAX310X_MODE2_ECHOSUPR_BIT,
MAX310X_MODE2_ECHOSUPR_BIT);
} else {
max310x_port_update(port, MAX310X_MODE1_REG,
MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
max310x_port_update(port, MAX310X_MODE2_REG,
MAX310X_MODE2_ECHOSUPR_BIT, 0);
}
rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
memset(rs485->padding, 0, sizeof(rs485->padding));
port->rs485 = *rs485;
return 0;
}
static void max310x_shutdown(struct uart_port *port)
{
struct max310x_port *s = dev_get_drvdata(port->dev);
/* Disable all interrupts */
max310x_port_write(port, MAX310X_IRQEN_REG, 0);
s->devtype->power(port, 0);
}
static int max310x_ioctl(struct uart_port *port, unsigned int cmd,
unsigned long arg)
{
#if defined(TIOCSRS485) && defined(TIOCGRS485)
struct serial_rs485 rs485;
unsigned int val;
switch (cmd) {
case TIOCSRS485:
if (copy_from_user(&rs485, (void __user *)arg, sizeof(rs485)))
return -EFAULT;
if (rs485.delay_rts_before_send > 0x0f ||
rs485.delay_rts_after_send > 0x0f)
return -ERANGE;
val = (rs485.delay_rts_before_send << 4) |
rs485.delay_rts_after_send;
max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
if (rs485.flags & SER_RS485_ENABLED) {
max310x_port_update(port, MAX310X_MODE1_REG,
MAX310X_MODE1_TRNSCVCTRL_BIT,
MAX310X_MODE1_TRNSCVCTRL_BIT);
max310x_port_update(port, MAX310X_MODE2_REG,
MAX310X_MODE2_ECHOSUPR_BIT,
MAX310X_MODE2_ECHOSUPR_BIT);
} else {
max310x_port_update(port, MAX310X_MODE1_REG,
MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
max310x_port_update(port, MAX310X_MODE2_REG,
MAX310X_MODE2_ECHOSUPR_BIT, 0);
}
return 0;
case TIOCGRS485:
memset(&rs485, 0, sizeof(rs485));
val = max310x_port_read(port, MAX310X_MODE1_REG);
rs485.flags = (val & MAX310X_MODE1_TRNSCVCTRL_BIT) ?
SER_RS485_ENABLED : 0;
rs485.flags |= SER_RS485_RTS_ON_SEND;
val = max310x_port_read(port, MAX310X_HDPIXDELAY_REG);
rs485.delay_rts_before_send = val >> 4;
rs485.delay_rts_after_send = val & 0x0f;
if (copy_to_user((void __user *)arg, &rs485, sizeof(rs485)))
return -EFAULT;
return 0;
default:
break;
}
#endif
return -ENOIOCTLCMD;
}
static void max310x_set_termios(struct uart_port *port,
struct ktermios *termios,
struct ktermios *old)
{
unsigned int lcr, flow = 0;
int baud;
/* Mask termios capabilities we don't support */
termios->c_cflag &= ~CMSPAR;
/* Word size */
switch (termios->c_cflag & CSIZE) {
case CS5:
lcr = MAX310X_LCR_WORD_LEN_5;
break;
case CS6:
lcr = MAX310X_LCR_WORD_LEN_6;
break;
case CS7:
lcr = MAX310X_LCR_WORD_LEN_7;
break;
case CS8:
default:
lcr = MAX310X_LCR_WORD_LEN_8;
break;
}
/* Parity */
if (termios->c_cflag & PARENB) {
lcr |= MAX310X_LCR_PARITY_BIT;
if (!(termios->c_cflag & PARODD))
lcr |= MAX310X_LCR_EVENPARITY_BIT;
}
/* Stop bits */
if (termios->c_cflag & CSTOPB)
lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
/* Update LCR register */
max310x_port_write(port, MAX310X_LCR_REG, lcr);
/* Set read status mask */
port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
if (termios->c_iflag & INPCK)
port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
MAX310X_LSR_FRERR_BIT;
if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
/* Set status ignore mask */
port->ignore_status_mask = 0;
if (termios->c_iflag & IGNBRK)
port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
if (!(termios->c_cflag & CREAD))
port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
MAX310X_LSR_RXOVR_BIT |
MAX310X_LSR_FRERR_BIT |
MAX310X_LSR_RXBRK_BIT;
/* Configure flow control */
max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
if (termios->c_cflag & CRTSCTS)
flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
MAX310X_FLOWCTRL_AUTORTS_BIT;
if (termios->c_iflag & IXON)
flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
MAX310X_FLOWCTRL_SWFLOWEN_BIT;
if (termios->c_iflag & IXOFF)
flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
MAX310X_FLOWCTRL_SWFLOWEN_BIT;
max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
/* Get baud rate generator configuration */
baud = uart_get_baud_rate(port, termios, old,
port->uartclk / 16 / 0xffff,
port->uartclk / 4);
/* Setup baudrate generator */
baud = max310x_set_baud(port, baud);
/* Update timeout according to new baud rate */
uart_update_timeout(port, termios->c_cflag, baud);
}
static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
struct regmap *regmap, int irq, unsigned long flags)
{
int i, ret, fmin, fmax, freq, uartclk;
struct clk *clk_osc, *clk_xtal;
struct max310x_port *s;
bool xtal = false;
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Alloc port structure */
s = devm_kzalloc(dev, sizeof(*s) +
sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
if (!s) {
dev_err(dev, "Error allocating port structure\n");
return -ENOMEM;
}
clk_osc = devm_clk_get(dev, "osc");
clk_xtal = devm_clk_get(dev, "xtal");
if (!IS_ERR(clk_osc)) {
s->clk = clk_osc;
fmin = 500000;
fmax = 35000000;
} else if (!IS_ERR(clk_xtal)) {
s->clk = clk_xtal;
fmin = 1000000;
fmax = 4000000;
xtal = true;
} else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
return -EPROBE_DEFER;
} else {
dev_err(dev, "Cannot get clock\n");
return -EINVAL;
}
ret = clk_prepare_enable(s->clk);
if (ret)
return ret;
freq = clk_get_rate(s->clk);
/* Check frequency limits */
if (freq < fmin || freq > fmax) {
ret = -ERANGE;
goto out_clk;
}
s->regmap = regmap;
s->devtype = devtype;
dev_set_drvdata(dev, s);
/* Check device to ensure we are talking to what we expect */
ret = devtype->detect(dev);
if (ret)
goto out_clk;
for (i = 0; i < devtype->nr; i++) {
unsigned int offs = i << 5;
/* Reset port */
regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
MAX310X_MODE2_RST_BIT);
/* Clear port reset */
regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
/* Wait for port startup */
do {
regmap_read(s->regmap,
MAX310X_BRGDIVLSB_REG + offs, &ret);
} while (ret != 0x01);
regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
MAX310X_MODE1_AUTOSLEEP_BIT,
MAX310X_MODE1_AUTOSLEEP_BIT);
}
uartclk = max310x_set_ref_clk(s, freq, xtal);
dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
/* Register UART driver */
s->uart.owner = THIS_MODULE;
s->uart.dev_name = "ttyMAX";
s->uart.major = MAX310X_MAJOR;
s->uart.minor = MAX310X_MINOR;
s->uart.nr = devtype->nr;
ret = uart_register_driver(&s->uart);
if (ret) {
dev_err(dev, "Registering UART driver failed\n");
goto out_clk;
}
#ifdef CONFIG_GPIOLIB
/* Setup GPIO cotroller */
s->gpio.owner = THIS_MODULE;
s->gpio.dev = dev;
s->gpio.label = dev_name(dev);
s->gpio.direction_input = max310x_gpio_direction_input;
s->gpio.get = max310x_gpio_get;
s->gpio.direction_output= max310x_gpio_direction_output;
s->gpio.set = max310x_gpio_set;
s->gpio.base = -1;
s->gpio.ngpio = devtype->nr * 4;
s->gpio.can_sleep = 1;
ret = gpiochip_add(&s->gpio);
if (ret)
goto out_uart;
#endif
mutex_init(&s->mutex);
for (i = 0; i < devtype->nr; i++) {
/* Initialize port data */
s->p[i].port.line = i;
s->p[i].port.dev = dev;
s->p[i].port.irq = irq;
s->p[i].port.type = PORT_MAX310X;
s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
s->p[i].port.iotype = UPIO_PORT;
s->p[i].port.iobase = i * 0x20;
s->p[i].port.membase = (void __iomem *)~0;
s->p[i].port.uartclk = uartclk;
s->p[i].port.rs485_config = max310x_rs485_config;
s->p[i].port.ops = &max310x_ops;
/* Disable all interrupts */
max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
/* Clear IRQ status register */
max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
/* Enable IRQ pin */
max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
MAX310X_MODE1_IRQSEL_BIT,
MAX310X_MODE1_IRQSEL_BIT);
/* Initialize queue for start TX */
INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
/* Initialize queue for changing mode */
INIT_WORK(&s->p[i].md_work, max310x_md_proc);
/* Register port */
uart_add_one_port(&s->uart, &s->p[i].port);
/* Go to suspend mode */
devtype->power(&s->p[i].port, 0);
}
/* Setup interrupt */
ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
IRQF_ONESHOT | flags, dev_name(dev), s);
if (!ret)
return 0;
dev_err(dev, "Unable to reguest IRQ %i\n", irq);
mutex_destroy(&s->mutex);
#ifdef CONFIG_GPIOLIB
gpiochip_remove(&s->gpio);
out_uart:
#endif
uart_unregister_driver(&s->uart);
out_clk:
clk_disable_unprepare(s->clk);
return ret;
}
