// Initialize max98090 codec device.
int max98090_device_init(Max98090Codec *codec)
{
// Reset the codec, the DSP core, and disable all interrupts.
if (max98090_reset(codec))
return 1;
uint8_t id;
if (max98090_i2c_read(codec, M98090_REG_REVISION_ID, &id))
return 1;
printf("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
/* Reading interrupt status to clear them */
int res = 0;
res = max98090_i2c_read(codec, M98090_REG_DEVICE_STATUS, &id);
res |= max98090_i2c_write(codec, M98090_REG_DAC_CONTROL,
M98090_DACHP_MASK);
res |= max98090_i2c_write(codec, M98090_REG_BIAS_CONTROL,
M98090_VCM_MODE_MASK);
res |= max98090_i2c_write(codec, M98090_REG_LEFT_SPK_MIXER, 0x1);
res |= max98090_i2c_write(codec, M98090_REG_RIGHT_SPK_MIXER, 0x2);
res |= max98090_i2c_write(codec, M98090_REG_LEFT_SPK_VOLUME, 0x25);
res |= max98090_i2c_write(codec, M98090_REG_RIGHT_SPK_VOLUME, 0x25);
res |= max98090_i2c_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0);
res |= max98090_i2c_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0);
res |= max98090_i2c_write(codec, M98090_REG_MASTER_MODE, 0x0);
res |= max98090_i2c_write(codec, M98090_REG_INTERFACE_FORMAT, 0x0);
res |= max98090_i2c_write(codec, M98090_REG_IO_CONFIGURATION,
M98090_SDIEN_MASK);
res |= max98090_i2c_write(codec, M98090_REG_DEVICE_SHUTDOWN,
M98090_SHDNN_MASK);
res |= max98090_i2c_write(codec, M98090_REG_OUTPUT_ENABLE,
M98090_HPREN_MASK | M98090_HPLEN_MASK |
M98090_SPREN_MASK | M98090_SPLEN_MASK |
M98090_DAREN_MASK | M98090_DALEN_MASK);
res |= max98090_i2c_write(codec, M98090_REG_IO_CONFIGURATION,
M98090_SDOEN_MASK | M98090_SDIEN_MASK);
return res;
}
static int max98090_probe(struct snd_soc_codec *codec)
{
struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
struct max98090_cdata *cdata;
int ret = 0;
ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
if (ret != 0) {
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
return ret;
}
codec->control_data = max98090->control_data;
codec->cache_sync = 1;
codec->write = max98090_i2c_write;
codec->read = max98090_i2c_read;
max98090->codec = codec;
/* reset the codec, the DSP core, and disable all interrupts */
max98090_reset(codec);
/* initialize private data */
max98090->sysclk = (unsigned)-1;
max98090->eq_textcnt = 0;
max98090->bq_textcnt = 0;
cdata = &max98090->dai;
cdata->rate = (unsigned)-1;
cdata->fmt = (unsigned)-1;
cdata->eq_sel = 0;
cdata->bq_sel = 0;
max98090->lin_state = 0;
max98090->mic1pre = 0;
max98090->mic2pre = 0;
ret = snd_soc_read(codec, M98090_0FF_REV_ID);
if (ret < 0) {
dev_err(codec->dev, "Failed to read device revision: %d\n",
ret);
goto err_access;
}
dev_info(codec->dev, "revision 0x%02x\n", ret);
snd_soc_write(codec, M98090_045_PWR_SYS, M98090_SHDNRUN);
/* initialize registers cache to hardware default */
max98090_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
snd_soc_write(codec, M98090_042_BIAS_CNTL, 0xF0);
snd_soc_write(codec, M98090_025_DAI_IOCFG, 0x07);
max98090_set_record_main_mic(codec);
snd_soc_update_bits(codec, M98090_045_PWR_SYS, M98090_SHDNRUN, M98090_SHDNRUN);
max98090_add_widgets(codec);
#if defined(CONFIG_MAX98090_HEADSET)
switch_dev_register(&switch_jack_detection);
INIT_DELAYED_WORK(&max98090->work, max98090_work);
schedule_delayed_work(&max98090->work, msecs_to_jiffies(6000));
#endif
err_access:
return ret;
}
