phys_size_t initdram(int board_type) { u32 dramsize = 0; /* * Check to see if the SDRAM has already been initialized * by a run control tool */ if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { u32 RC, temp; RC = (CONFIG_SYS_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* Initialize DRAM Control Register: DCR */ mbar_writeShort(MCFSIM_DCR, (0x8400 | RC)); __asm__("nop"); mbar_writeLong(MCFSIM_DACR0, 0x00003224); __asm__("nop"); /* Initialize DMR0 */ dramsize = (CONFIG_SYS_SDRAM_SIZE << 20); temp = (dramsize - 1) & 0xFFFC0000; mbar_writeLong(MCFSIM_DMR0, temp | 1); __asm__("nop"); mbar_writeLong(MCFSIM_DACR0, 0x0000322c); mb(); __asm__("nop"); /* Write to this block to initiate precharge */ *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; mb(); __asm__("nop"); /* Set RE bit in DACR */ mbar_writeLong(MCFSIM_DACR0, mbar_readLong(MCFSIM_DACR0) | 0x8000); __asm__("nop"); /* Wait for at least 8 auto refresh cycles to occur */ udelay(500); /* Finish the configuration by issuing the MRS */ mbar_writeLong(MCFSIM_DACR0, mbar_readLong(MCFSIM_DACR0) | 0x0040); __asm__("nop"); *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; mb(); }
void mcf_timer_interrupt (void * not_used){ volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); /* check for timer 2 interrupts */ if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) { return; } /* reset timer */ timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; timestamp ++; }
int print_cpuinfo(void) { char buf[32]; unsigned char resetsource = mbar_readLong(SIM_RSR); printf("CPU: Freescale Coldfire MCF5253 at %s MHz\n", strmhz(buf, CONFIG_SYS_CLK)); if ((resetsource & SIM_RSR_HRST) || (resetsource & SIM_RSR_SWTR)) { printf("Reset:%s%s\n", (resetsource & SIM_RSR_HRST) ? " Hardware/ System Reset" : "", (resetsource & SIM_RSR_SWTR) ? " Software Watchdog" : ""); } return 0; }
void timer_init (void) { volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); timestamp = 0; /* Set up TIMER 2 as clock */ timerp->timer_tmr = MCFTIMER_TMR_DISABLE; /* initialize and enable timer 2 interrupt */ irq_install_handler (31, mcf_timer_interrupt, 0); mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3); timerp->timer_tcn = 0; timerp->timer_trr = 1000; /* Interrupt every ms */ /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; }
void dtimer_intr_setup(void) { mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); }