static inline int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; u32 enable = mbox_read_reg(p->irqenable); u32 status = mbox_read_reg(p->irqstatus); return (enable & status & bit); }
/* Mailbox H/W preparations */ static int omap2_mbox_startup(struct omap_mbox *mbox) { u32 l; unsigned long timeout; if (!cpu_is_omap44xx()) { mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); if (IS_ERR(mbox_ick_handle)) { printk(KERN_ERR "Could not get mailboxes_ick: %ld\n", PTR_ERR(mbox_ick_handle)); return PTR_ERR(mbox_ick_handle); } clk_enable(mbox_ick_handle); } if (cpu_is_omap44xx()) { mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG); timeout = jiffies + msecs_to_jiffies(20); do { l = mbox_read_reg(MAILBOX_SYSCONFIG); if (!(l & OMAP4_SOFTRESET)) break; } while (!time_after(jiffies, timeout)); if (l & OMAP4_SOFTRESET) { pr_err("Can't take mailbox out of reset\n"); return -ENODEV; } } else { mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG); timeout = jiffies + msecs_to_jiffies(20); do { l = mbox_read_reg(MAILBOX_SYSSTATUS); if (l & RESETDONE) break; } while (!time_after(jiffies, timeout)); if (!(l & RESETDONE)) { pr_err("Can't take mailbox out of reset\n"); return -ENODEV; } } l = mbox_read_reg(MAILBOX_REVISION); pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); if (cpu_is_omap44xx()) l = OMAP4_SMARTIDLE; else l = SMARTIDLE | AUTOIDLE; mbox_write_reg(l, MAILBOX_SYSCONFIG); omap2_mbox_enable_irq(mbox, IRQ_RX); return 0; }
/* msg */ static mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox) { struct omap_mbox1_fifo *fifo = &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; mbox_msg_t msg; msg = mbox_read_reg(fifo->data); msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16; return msg; }
static int omap1_mbox_fifo_full(struct omap_mbox *mbox) { struct omap_mbox1_fifo *fifo = &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo; return mbox_read_reg(fifo->flag); }
static void omap2_mbox_save_ctx(struct omap_mbox *mbox) { int i, j; /* Save irqs per user */ for (j = 0, i = 0; j < nr_mbox_users; i++, j++) { if (cpu_is_omap44xx()) mbox_ctx[i] = mbox_read_reg(OMAP4_MAILBOX_IRQENABLE(j)); else mbox_ctx[i] = mbox_read_reg(MAILBOX_IRQENABLE(j)); dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, i, mbox_ctx[i]); } // omap2_mbox_shutdown(mbox); }
static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; l = mbox_read_reg(p->irqdisable); l &= ~bit; mbox_write_reg(l, p->irqdisable); }
static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; mbox_write_reg(bit, p->irqstatus); /* Flush posted write for irq status to avoid spurious interrupts */ mbox_read_reg(p->irqstatus); }
static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq) { struct omap_mbox2_priv *p = mbox->priv; u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit; if (!cpu_is_omap44xx()) bit = mbox_read_reg(p->irqdisable) & ~bit; mbox_write_reg(bit, p->irqdisable); }
/* Mailbox H/W preparations */ static int omap2_mbox_startup(struct omap_mbox *mbox) { u32 l; pm_runtime_enable(mbox->dev->parent); pm_runtime_get_sync(mbox->dev->parent); l = mbox_read_reg(MAILBOX_REVISION); pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); return 0; }
/* Mailbox H/W preparations */ static int omap2_mbox_startup(struct omap_mbox *mbox) { unsigned int l; mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); if (IS_ERR(mbox_ick_handle)) { printk("Could not get mailboxes_ick\n"); return -ENODEV; } clk_enable(mbox_ick_handle); l = mbox_read_reg(MAILBOX_REVISION); pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); /* set smart-idle & autoidle */ l = mbox_read_reg(MAILBOX_SYSCONFIG); l |= 0x00000011; mbox_write_reg(l, MAILBOX_SYSCONFIG); omap2_mbox_enable_irq(mbox, IRQ_RX); return 0; }
static void omap2_mbox_save_ctx(struct omap_mbox *mbox) { int i; struct omap_mbox2_priv *p = mbox->priv; for (i = 0; i < MBOX_REG_SIZE; i += sizeof(u32)) { u32 val; val = mbox_read_reg(i); *(u32 *)(p->ctx + i) = val; dev_dbg(mbox->dev, "%s\t[%02d] %08x\n", __func__, i, val); } }
static void omap2_mbox_save_ctx(struct omap_mbox *mbox) { int i; struct omap_mbox2_priv *p = mbox->priv; int nr_regs; if (cpu_is_omap44xx()) nr_regs = OMAP4_MBOX_NR_REGS; else nr_regs = MBOX_NR_REGS; for (i = 0; i < nr_regs; i++) { p->ctx[i] = mbox_read_reg(i * sizeof(u32)); dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, i, p->ctx[i]); } }
/* Mailbox H/W preparations */ static inline int omap2_mbox_startup(struct omap_mbox *mbox) { unsigned int l; mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); if (IS_ERR(mbox_ick_handle)) { printk("Could not get mailboxes_ick\n"); return -ENODEV; } clk_enable(mbox_ick_handle); /* set smart-idle & autoidle */ l = mbox_read_reg(MAILBOX_SYSCONFIG); l |= 0x00000011; mbox_write_reg(l, MAILBOX_SYSCONFIG); return 0; }
static int omap2_mbox_fifo_full(struct omap_mbox *mbox) { struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; return mbox_read_reg(fifo->fifo_stat); }
static int omap2_mbox_fifo_empty(struct omap_mbox *mbox) { struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; return (mbox_read_reg(fifo->msg_stat) == 0); }
/* Mailbox FIFO handle functions */ static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox) { struct omap_mbox2_fifo *fifo = &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; return (mbox_msg_t) mbox_read_reg(fifo->msg); }