int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/*
* Map SPI devices via MBUS so that they can be accessed via
* the SPI direct access mode
*/
mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
return 0;
}
int board_init(void)
{
int ret;
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/*
* Map SPI devices via MBUS so that they can be accessed via
* the SPI direct access mode
*/
mbus_dt_setup_win(&mbus_state, SPI_BUS0_DEV1_BASE, SPI_BUS0_DEV1_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI0_CS1);
mbus_dt_setup_win(&mbus_state, SPI_BUS1_DEV2_BASE, SPI_BUS0_DEV1_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPI1_CS2);
/*
* Set RX Channel Control 0 Register:
* Tests have shown, that setting the LPF_COEF from 0 (1/8)
* to 3 (1/1) results in a more stable USB connection.
*/
setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 1), 0xc);
setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 2), 0xc);
setbits_le32(PHY_CHANNEL_RX_CTRL0_REG(0, 3), 0xc);
/* Toggle USB power */
ret = gpio_request(GPIO_USB0_PWR_ON, "USB0_PWR_ON");
if (ret < 0)
return ret;
gpio_direction_output(GPIO_USB0_PWR_ON, 0);
ret = gpio_request(GPIO_USB1_PWR_ON, "USB1_PWR_ON");
if (ret < 0)
return ret;
gpio_direction_output(GPIO_USB1_PWR_ON, 0);
mdelay(1);
gpio_set_value(GPIO_USB0_PWR_ON, 1);
gpio_set_value(GPIO_USB1_PWR_ON, 1);
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
/* window for NVS */
mbus_dt_setup_win(&mbus_state, CONFIG_NVS_LOCATION, CONFIG_NVS_SIZE,
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1);
/* DEV_READYn is not needed for NVS, ignore it when accessing CS1 */
writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8);
return 0;
}
