static void mcclock_isa_attach(device_t parent, device_t self, void *aux) { struct mc146818_softc *sc = device_private(self); struct isa_attach_args *ia = aux; sc->sc_dev = self; sc->sc_bst = ia->ia_iot; if (bus_space_map(sc->sc_bst, ia->ia_io[0].ir_addr, ia->ia_io[0].ir_size, 0, &sc->sc_bsh)) panic("mcclock_isa_attach: couldn't map clock I/O space"); sc->sc_year0 = ALGOR_YEAR_ZERO; sc->sc_flag = MC146818_NO_CENT_ADJUST; sc->sc_mcread = mcclock_isa_read; sc->sc_mcwrite = mcclock_isa_write; sc->sc_getcent = NULL; sc->sc_setcent = NULL; /* * Turn interrupts off, just in case. Need to leave the SQWE * set, because that's the DRAM refresh signal on Rev. B boards. */ mcclock_isa_write(sc, MC_REGB, MC_REGB_SQWE | MC_REGB_BINARY | MC_REGB_24HR); mc146818_attach(sc); aprint_normal("\n"); }
void mcclock_isa_attach(device_t parent, device_t self, void *aux) { struct mc146818_softc *sc = device_private(self); struct isa_attach_args *ia = aux; sc->sc_dev = self; sc->sc_bst = ia->ia_iot; if (bus_space_map(sc->sc_bst, ia->ia_io[0].ir_addr, ia->ia_io[0].ir_size, 0, &sc->sc_bsh)) { aprint_error(": can't map registers!\n"); return; } /* * Select a 32KHz crystal, periodic interrupt every 1024 Hz. * XXX: We disable periodic interrupts, so why set a rate? */ mcclock_isa_write(sc, MC_REGA, MC_BASE_32_KHz | MC_RATE_1024_Hz); /* * 24 Hour clock, no interrupts please. */ mcclock_isa_write(sc, MC_REGB, MC_REGB_24HR); sc->sc_year0 = 1900; sc->sc_flag = 0; sc->sc_mcread = mcclock_isa_read; sc->sc_mcwrite = mcclock_isa_write; #if 0 /* * XXX: perhaps on some systems we should manage the century byte? * For now we don't worry about it. (Ugly MD code.) */ sc->sc_getcent = mcclock_isa_getcent; sc->sc_setcent = mcclock_isa_setcent; #endif mc146818_attach(sc); aprint_normal("\n"); }