static void pyr_dsi_dbi_mode_set(struct drm_encoder * encoder,
struct drm_display_mode * mode,
struct drm_display_mode * adjusted_mode)
{
int ret = 0;
struct drm_device * dev = encoder->dev;
struct drm_psb_private * dev_priv = (struct drm_psb_private*)dev->dev_private;
struct mdfld_dsi_encoder * dsi_encoder = MDFLD_DSI_ENCODER(encoder);
struct mdfld_dsi_dbi_output * dsi_output = MDFLD_DSI_DBI_OUTPUT(dsi_encoder);
struct mdfld_dsi_config * dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder);
struct mdfld_dsi_connector * dsi_connector = dsi_config->connector;
int pipe = dsi_connector->pipe;
u8 param = 0;
/*regs*/
u32 mipi_reg = MIPI;
u32 dspcntr_reg = DSPACNTR;
u32 pipeconf_reg = PIPEACONF;
u32 reg_offset = 0;
/*values*/
u32 dspcntr_val = dev_priv->dspcntr;
u32 pipeconf_val = dev_priv->pipeconf;
u32 h_active_area = mode->hdisplay;
u32 v_active_area = mode->vdisplay;
u32 mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX);
if (dev_priv->platform_rev_id != MDFLD_PNW_A0)
mipi_val = (PASS_FROM_SPHY_TO_AFE | TE_TRIGGER_GPIO_PIN);
PSB_DEBUG_ENTRY("mipi_val =0x%x\n", mipi_val);
PSB_DEBUG_ENTRY("type %s\n", (pipe == 2) ? "MIPI2" : "MIPI");
PSB_DEBUG_ENTRY("h %d v %d\n", mode->hdisplay, mode->vdisplay);
if(pipe == 2) {
mipi_reg = MIPI_C;
dspcntr_reg = DSPCCNTR;
pipeconf_reg = PIPECCONF;
reg_offset = MIPIC_REG_OFFSET;
dspcntr_val = dev_priv->dspcntr2;
pipeconf_val = dev_priv->pipeconf2;
} else {
mipi_val |= 0x2; /*two lanes for port A and C respectively*/
}
if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, OSPM_UHB_FORCE_POWER_ON)) {
DRM_ERROR("hw begin failed\n");
return;
}
/*set up pipe related registers*/
REG_WRITE(mipi_reg, mipi_val);
REG_READ(mipi_reg);
pyr_dsi_controller_dbi_init(dsi_config, pipe);
msleep(20);
REG_WRITE(dspcntr_reg, dspcntr_val);
REG_READ(dspcntr_reg);
/*20ms delay before sending exit_sleep_mode*/
msleep(20);
/*send exit_sleep_mode DCS*/
ret = mdfld_dsi_dbi_send_dcs(dsi_output, exit_sleep_mode, NULL, 0, CMD_DATA_SRC_SYSTEM_MEM);
if(ret) {
DRM_ERROR("sent exit_sleep_mode faild\n");
goto out_err;
}
if (dev_priv->platform_rev_id != MDFLD_PNW_A0) {
/*send set_tear_on DCS*/
ret = mdfld_dsi_dbi_send_dcs(dsi_output, set_tear_on, ¶m, 1, CMD_DATA_SRC_SYSTEM_MEM);
if(ret) {
DRM_ERROR("%s - sent set_tear_on faild\n", __func__);
goto out_err;
}
}
/*do some init stuff*/
mdfld_dsi_brightness_init(dsi_config, pipe);
mdfld_dsi_gen_fifo_ready (dev, (MIPIA_GEN_FIFO_STAT_REG + reg_offset), HS_CTRL_FIFO_EMPTY | HS_DATA_FIFO_EMPTY);
REG_WRITE(pipeconf_reg, pipeconf_val | PIPEACONF_DSR);
REG_READ(pipeconf_reg);
/*TODO: this looks ugly, try to move it to CRTC mode setting*/
if(pipe == 2) {
dev_priv->pipeconf2 |= PIPEACONF_DSR;
} else {
dev_priv->pipeconf |= PIPEACONF_DSR;
}
PSB_DEBUG_ENTRY("pipeconf %x\n", REG_READ(pipeconf_reg));
ret = mdfld_dsi_dbi_update_area(dsi_output, 0, 0, h_active_area - 1, v_active_area - 1);
if(ret) {
DRM_ERROR("update area failed\n");
goto out_err;
}
out_err:
ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
if(ret) {
DRM_ERROR("mode set failed\n");
} else {
PSB_DEBUG_ENTRY("mode set done successfully\n");
}
}
void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_encoder *dsi_encoder = mdfld_dsi_encoder(encoder);
struct mdfld_dsi_dpi_output *dpi_output =
MDFLD_DSI_DPI_OUTPUT(dsi_encoder);
struct mdfld_dsi_config *dsi_config =
mdfld_dsi_encoder_get_config(dsi_encoder);
struct drm_device *dev = dsi_config->dev;
struct drm_psb_private *dev_priv = dev->dev_private;
int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
u32 pipeconf_reg = PIPEACONF;
u32 dspcntr_reg = DSPACNTR;
u32 pipeconf;
u32 dspcntr;
u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX;
if (pipe == -1)
return;
pipeconf = dev_priv->pipeconf[pipe];
dspcntr = dev_priv->dspcntr[pipe];
if (pipe) {
pipeconf_reg = PIPECCONF;
dspcntr_reg = DSPCCNTR;
} else {
if (mdfld_get_panel_type(dev, pipe) == TC35876X)
mipi &= (~0x03); /* Use all four lanes */
else
mipi |= 2;
}
/*start up display island if it was shutdown*/
if (!gma_power_begin(dev, true))
return;
if (mdfld_get_panel_type(dev, pipe) == TC35876X) {
/*
* The following logic is required to reset the bridge and
* configure. This also starts the DSI clock at 200MHz.
*/
tc35876x_set_bridge_reset_state(dev, 0); /*Pull High Reset */
tc35876x_toshiba_bridge_panel_on(dev);
udelay(100);
/* Now start the DSI clock */
REG_WRITE(MRST_DPLL_A, 0x00);
REG_WRITE(MRST_FPA0, 0xC1);
REG_WRITE(MRST_DPLL_A, 0x00800000);
udelay(500);
REG_WRITE(MRST_DPLL_A, 0x80800000);
if (REG_BIT_WAIT(pipeconf_reg, 1, 29))
dev_err(&dev->pdev->dev, "%s: DSI PLL lock timeout\n",
__func__);
REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008);
mipi_set_properties(dsi_config, pipe);
mdfld_mipi_config(dsi_config, pipe);
mdfld_set_pipe_timing(dsi_config, pipe);
REG_WRITE(DSPABASE, 0x00);
REG_WRITE(DSPASIZE,
((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
REG_WRITE(DSPACNTR, 0x98000000);
REG_WRITE(DSPASURF, 0x00);
REG_WRITE(VGACNTRL, 0x80000000);
REG_WRITE(DEVICE_READY_REG, 0x00000001);
REG_WRITE(MIPI_PORT_CONTROL(pipe), 0x80810000);
} else {
/*set up mipi port FIXME: do at init time */
REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi);
}
REG_READ(MIPI_PORT_CONTROL(pipe));
if (mdfld_get_panel_type(dev, pipe) == TMD_VID) {
/* NOP */
} else if (mdfld_get_panel_type(dev, pipe) == TC35876X) {
/* set up DSI controller DPI interface */
mdfld_dsi_dpi_controller_init(dsi_config, pipe);
/* Configure MIPI Bridge and Panel */
tc35876x_configure_lvds_bridge(dev);
dev_priv->dpi_panel_on[pipe] = true;
} else {
/*turn on DPI interface*/
mdfld_dsi_dpi_turn_on(dpi_output, pipe);
}
/*set up pipe*/
REG_WRITE(pipeconf_reg, pipeconf);
REG_READ(pipeconf_reg);
/*set up display plane*/
REG_WRITE(dspcntr_reg, dspcntr);
REG_READ(dspcntr_reg);
msleep(20); /* FIXME: this should wait for vblank */
if (mdfld_get_panel_type(dev, pipe) == TMD_VID) {
/* NOP */
} else if (mdfld_get_panel_type(dev, pipe) == TC35876X) {
mdfld_dsi_dpi_turn_on(dpi_output, pipe);
} else {
/* init driver ic */
mdfld_dsi_tpo_ic_init(dsi_config, pipe);
/*init backlight*/
mdfld_dsi_brightness_init(dsi_config, pipe);
}
gma_power_end(dev);
}
void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode)
{
struct mdfld_dsi_encoder *dsi_encoder = MDFLD_DSI_ENCODER(encoder);
struct mdfld_dsi_dpi_output *dpi_output = MDFLD_DSI_DPI_OUTPUT(dsi_encoder);
struct mdfld_dsi_config *dsi_config = mdfld_dsi_encoder_get_config(dsi_encoder);
struct drm_device *dev = dsi_config->dev;
struct drm_psb_private *dev_priv = dev->dev_private;
int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder);
u32 pipeconf_reg = PIPEACONF;
u32 dspcntr_reg = DSPACNTR;
u32 mipi_reg = MIPI;
u32 reg_offset = 0;
u32 pipeconf = dev_priv->pipeconf;
u32 dspcntr = dev_priv->dspcntr;
u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX;
dev_dbg(dev->dev, "set mode %dx%d on pipe %d\n",
mode->hdisplay, mode->vdisplay, pipe);
if(pipe) {
pipeconf_reg = PIPECCONF;
dspcntr_reg = DSPCCNTR;
mipi_reg = MIPI_C;
reg_offset = MIPIC_REG_OFFSET;
} else {
mipi |= 2;
}
if (!gma_power_begin(dev, true))
return;
/* Set up mipi port FIXME: do at init time */
REG_WRITE(mipi_reg, mipi);
REG_READ(mipi_reg);
/* Set up DSI controller DPI interface */
mdfld_dsi_dpi_controller_init(dsi_config, pipe);
if (mdfld_get_panel_type(dev, pipe) != TMD_VID) {
/* Turn on DPI interface */
mdfld_dsi_dpi_turn_on(dpi_output, pipe);
}
/* Set up pipe */
REG_WRITE(pipeconf_reg, pipeconf);
REG_READ(pipeconf_reg);
/* Set up display plane */
REG_WRITE(dspcntr_reg, dspcntr);
REG_READ(dspcntr_reg);
msleep(20); /* FIXME: this should wait for vblank */
dev_dbg(dev->dev, "State %x, power %d\n",
REG_READ(MIPIA_INTR_STAT_REG + reg_offset),
dpi_output->panel_on);
if (mdfld_get_panel_type(dev, pipe) != TMD_VID) {
/* Init driver ic */
mdfld_dsi_tpo_ic_init(dsi_config, pipe);
/* Init backlight */
mdfld_dsi_brightness_init(dsi_config, pipe);
}
gma_power_end(dev);
}