/* Utility to send the preamble, address, and
* register (common to read and write).
*/
static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int read, u8 phy, u8 reg)
{
const struct mdiobb_ops *ops = ctrl->ops;
int i;
ops->set_mdio_dir(ctrl, 1);
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good
* measure. The IEEE spec says this is a PHY optional
* requirement. The AMD 79C874 requires one after power up and
* one after a MII communications error. This means that we are
* doing more preambles than we need, but it is safer and will be
* much more robust.
*/
for (i = 0; i < 32; i++)
mdiobb_send_bit(ctrl, 1);
/* send the start bit (01) and the read opcode (10) or write (10) */
mdiobb_send_bit(ctrl, 0);
mdiobb_send_bit(ctrl, 1);
mdiobb_send_bit(ctrl, read);
mdiobb_send_bit(ctrl, !read);
mdiobb_send_num(ctrl, phy, 5);
mdiobb_send_num(ctrl, reg, 5);
}
/* Utility to send the preamble, address, and
* register (common to read and write).
*/
static void mdiobb_cmd(int read, u8 phy, u8 reg)
{
int i;
gpio_direction_output(MDIO, 1);
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good
* measure. The IEEE spec says this is a PHY optional
* requirement. The AMD 79C874 requires one after power up and
* one after a MII communications error. This means that we are
* doing more preambles than we need, but it is safer and will be
* much more robust.
*/
for (i = 0; i < 32; i++)
mdiobb_send_bit(1);
/* send the start bit (01) and the read opcode (10) or write (10) */
mdiobb_send_bit(0);
mdiobb_send_bit(1);
mdiobb_send_bit(read);
mdiobb_send_bit(!read);
mdiobb_send_num(phy, 5);
mdiobb_send_num(reg, 5);
}
static int mdiobb_write(struct mii_bus *bus, int phy, int reg, u16 val)
{
struct mdiobb_ctrl *ctrl = bus->priv;
mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg);
/* send the turnaround (10) */
mdiobb_send_bit(ctrl, 1);
mdiobb_send_bit(ctrl, 0);
mdiobb_send_num(ctrl, val, 16);
ctrl->ops->set_mdio_dir(ctrl, 0);
mdiobb_get_bit(ctrl);
return 0;
}
/* In clause 45 mode all commands are prefixed by MDIO_ADDR to specify the
lower 16 bits of the 21 bit address. This transfer is done identically to a
MDIO_WRITE except for a different code. To enable clause 45 mode or
MII_ADDR_C45 into the address. Theoretically clause 45 and normal devices
can exist on the same bus. Normal devices should ignore the MDIO_ADDR
phase. */
static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr)
{
unsigned int dev_addr = (addr >> 16) & 0x1F;
unsigned int reg = addr & 0xFFFF;
mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, dev_addr);
/* send the turnaround (10) */
mdiobb_send_bit(ctrl, 1);
mdiobb_send_bit(ctrl, 0);
mdiobb_send_num(ctrl, reg, 16);
ctrl->ops->set_mdio_dir(ctrl, 0);
mdiobb_get_bit(ctrl);
return dev_addr;
}
int mdiobb_write(int phy_base, int phy, int reg, u16 val)
{
/*
* Get Right Phy Address
*/
phy = phy + phy_base;
mdiobb_cmd(MDIO_WRITE, phy, reg);
/* send the turnaround (10) */
mdiobb_send_bit(1);
mdiobb_send_bit(0);
mdiobb_send_num(val, 16);
gpio_direction_input(MDIO);
return 0;
}
