/* * mdp4_dmap_done_dsi_video: called from isr */ void mdp4_dmap_done_dsi_video(int cndx) { struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; if (cndx >= MAX_CONTROLLER) { pr_err("%s: out or range: cndx=%d\n", __func__, cndx); return; } vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; spin_lock(&vctrl->spin_lock); vsync_irq_disable(INTR_DMA_P_DONE, MDP_DMAP_TERM); if (pipe == NULL) { spin_unlock(&vctrl->spin_lock); return; } if (vctrl->blt_change) { mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmap_xy(pipe); vctrl->blt_change = 0; } complete_all(&vctrl->dmap_comp); mdp4_overlay_dma_commit(cndx); spin_unlock(&vctrl->spin_lock); }
/* * mdp4_dmap_done_dsi_video: called from isr */ void mdp4_dmap_done_dsi_video(int cndx) { struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; if (cndx >= MAX_CONTROLLER) { pr_err("%s: out or range: cndx=%d\n", __func__, cndx); return; } vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; spin_lock(&vctrl->spin_lock); vsync_irq_disable(INTR_DMA_P_DONE, MDP_DMAP_TERM); if (vctrl->blt_change) { mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmap_xy(pipe); if (pipe->ov_blt_addr) { mdp4_dsi_video_blt_ov_update(pipe); pipe->ov_cnt++; /* Prefill one frame */ vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM); /* kickoff overlay0 engine */ mdp4_stat.kickoff_ov0++; vctrl->ov_koff++; /* make up for prefill */ outpdw(MDP_BASE + 0x0004, 0); } vctrl->blt_change = 0; } complete_all(&vctrl->dmap_comp); mdp4_overlay_dma_commit(cndx); spin_unlock(&vctrl->spin_lock); }
void mdp4_dmae_done_dtv(void) { int cndx; struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; cndx = 0; if (cndx >= MAX_CONTROLLER) { pr_err("%s: out or range: cndx=%d\n", __func__, cndx); return; } vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; if (pipe == NULL) return; pr_debug("%s: cpu=%d\n", __func__, smp_processor_id()); spin_lock(&vctrl->spin_lock); if (vctrl->blt_change) { if (pipe->ov_blt_addr) { mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmae_xy(pipe); mdp4_dtv_blt_ov_update(pipe); pipe->blt_ov_done++; vsync_irq_enable(INTR_OVERLAY1_DONE, MDP_OVERLAY1_TERM); mdp4_stat.kickoff_ov1++; outpdw(MDP_BASE + 0x0008, 0); } vctrl->blt_change = 0; } if (mdp_rev <= MDP_REV_41) mdp4_mixer_blend_cfg(MDP4_MIXER1); complete_all(&vctrl->dmae_comp); mdp4_overlay_dma_commit(MDP4_MIXER1); vsync_irq_disable(INTR_DMA_E_DONE, MDP_DMA_E_TERM); spin_unlock(&vctrl->spin_lock); }
/* * mdp4_dma_p_done_lcdc: called from isr */ void mdp4_dmap_done_lcdc(int cndx) { struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; if (cndx >= MAX_CONTROLLER) { pr_err("%s: out or range: cndx=%d\n", __func__, cndx); return; } vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; #if defined (CONFIG_EUR_MODEL_GT_I9210) if (pipe == NULL) return; #endif spin_lock(&vctrl->spin_lock); vsync_irq_disable(INTR_DMA_P_DONE, MDP_DMAP_TERM); if (vctrl->blt_change) { mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmap_xy(pipe); if (pipe->ov_blt_addr) { mdp4_lcdc_blt_ov_update(pipe); pipe->ov_cnt++; /* Prefill one frame */ vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM); /* kickoff overlay0 engine */ mdp4_stat.kickoff_ov0++; vctrl->ov_koff++; /* make up for prefill */ outpdw(MDP_BASE + 0x0004, 0); } vctrl->blt_change = 0; } complete_all(&vctrl->dmap_comp); if (mdp_rev <= MDP_REV_41 && pipe->ov_blt_addr == 0) mdp4_mixer_blend_cfg(MDP4_MIXER0); mdp4_overlay_dma_commit(cndx); spin_unlock(&vctrl->spin_lock); }
/* * mdp4_dmae_done_dtv: called from isr */ void mdp4_dmae_done_dtv(void) { int cndx; struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; cndx = 0; if (cndx >= MAX_CONTROLLER) { pr_err("%s: out or range: cndx=%d\n", __func__, cndx); return; } vctrl = &vsync_ctrl_db[cndx]; pipe = vctrl->base_pipe; spin_lock(&vctrl->spin_lock); if (vctrl->blt_change) { if (pipe->ov_blt_addr) { mdp4_overlayproc_cfg(pipe); mdp4_overlay_dmae_xy(pipe); mdp4_dtv_blt_ov_update(pipe); pipe->blt_ov_done++; /* Prefill one frame */ vsync_irq_enable(INTR_OVERLAY1_DONE, MDP_OVERLAY1_TERM); /* kickoff overlay1 engine */ mdp4_stat.kickoff_ov1++; outpdw(MDP_BASE + 0x0008, 0); } vctrl->blt_change = 0; } vctrl->dmae_intr_cnt--; if (vctrl->dmae_wait_cnt) { complete_all(&vctrl->dmae_comp); vctrl->dmae_wait_cnt = 0; /* reset */ } else { mdp4_overlay_dma_commit(MDP4_MIXER1); } vsync_irq_disable(INTR_DMA_E_DONE, MDP_DMA_E_TERM); spin_unlock(&vctrl->spin_lock); }
void mdp4_dmap_done_dsi_cmd(int cndx) { struct vsycn_ctrl *vctrl; struct mdp4_overlay_pipe *pipe; int diff; vsync_irq_disable(INTR_DMA_P_DONE, MDP_DMAP_TERM); vctrl = &vsync_ctrl_db[cndx]; vctrl->dmap_intr_tot++; pipe = vctrl->base_pipe; if (pipe->ov_blt_addr == 0) { mdp4_overlay_dma_commit(cndx); return; } /* blt enabled */ spin_lock(&vctrl->spin_lock); pipe->blt_dmap_done++; diff = pipe->blt_ov_done - pipe->blt_dmap_done; spin_unlock(&vctrl->spin_lock); pr_debug("%s: ov_done=%d dmap_done=%d ov_koff=%d dmap_koff=%d\n", __func__, pipe->blt_ov_done, pipe->blt_dmap_done, pipe->blt_ov_koff, pipe->blt_dmap_koff); if (diff <= 0) { if (pipe->blt_end) { pipe->blt_end = 0; pipe->ov_blt_addr = 0; pipe->dma_blt_addr = 0; pipe->blt_changed = 1; pr_info("%s: BLT-END\n", __func__); } } spin_unlock(&dsi_clk_lock); }