void mdp4_mddi_overlay(struct msm_fb_data_type *mfd)
{
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
unsigned long flags;
mutex_lock(&mfd->dma->ov_mutex);
vctrl = &vsync_ctrl_db[cndx];
if (!mfd->panel_power_on) {
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
pipe = vctrl->base_pipe;
if (pipe == NULL) {
pr_err("%s: NO base pipe\n", __func__);
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
mutex_lock(&vctrl->update_lock);
if (!vctrl->clk_enabled) {
pr_err("%s: mdp clocks disabled\n", __func__);
mutex_unlock(&vctrl->update_lock);
mutex_unlock(&mfd->dma->ov_mutex);
return;
}
mutex_unlock(&vctrl->update_lock);
spin_lock_irqsave(&vctrl->spin_lock, flags);
/*
* in the middle of shutting clocks down
* delay to allow pan display to go through
*/
vctrl->expire_tick = VSYNC_EXPIRE_TICK;
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
if (pipe->mixer_stage == MDP4_MIXER_STAGE_BASE) {
mdp4_mddi_vsync_enable(mfd, pipe, 0);
mdp4_overlay_setup_pipe_addr(mfd, pipe);
mdp4_mddi_pipe_queue(0, pipe);
}
mdp4_overlay_mdp_pipe_req(pipe, mfd);
mdp4_overlay_mdp_perf_req(mfd, pipe);
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_mddi_pipe_commit();
mdp4_overlay_mdp_perf_upd(mfd, 0);
mutex_unlock(&mfd->dma->ov_mutex);
}
void mdp4_atv_overlay(struct msm_fb_data_type *mfd)
{
struct fb_info *fbi = mfd->fbi;
uint8 *buf;
unsigned int buf_offset;
int bpp;
unsigned long flag;
struct mdp4_overlay_pipe *pipe;
if (!mfd->panel_power_on)
return;
/* */
bpp = fbi->var.bits_per_pixel / 8;
buf = (uint8 *) fbi->fix.smem_start;
buf_offset = calc_fb_offset(mfd, fbi, bpp);
mutex_lock(&mfd->dma->ov_mutex);
pipe = atv_pipe;
if (mfd->map_buffer) {
pipe->srcp0_addr = (unsigned int)mfd->map_buffer->iova[0] + \
buf_offset;
pr_debug("start 0x%lx srcp0_addr 0x%x\n", mfd->
map_buffer->iova[0], pipe->srcp0_addr);
} else {
pipe->srcp0_addr = (uint32)(buf + buf_offset);
}
mdp_update_pm(mfd, vsync_ctrl_db[0].vsync_time);
mdp4_overlay_mdp_perf_req(pipe, mfd);
mdp4_overlay_mdp_perf_upd(mfd, 1);
mdp4_overlay_rgb_setup(pipe);
mdp4_overlay_reg_flush(pipe, 0);
mdp4_mixer_stage_up(pipe, 0);
mdp4_mixer_stage_commit(pipe->mixer_num);
printk(KERN_INFO "mdp4_atv_overlay: pipe=%x ndx=%d\n",
(int)pipe, pipe->pipe_ndx);
/* */
spin_lock_irqsave(&mdp_spin_lock, flag);
mdp_enable_irq(MDP_OVERLAY1_TERM);
INIT_COMPLETION(atv_pipe->comp);
mfd->dma->waiting = TRUE;
outp32(MDP_INTR_CLEAR, INTR_OVERLAY1_DONE);
mdp_intr_mask |= INTR_OVERLAY1_DONE;
outp32(MDP_INTR_ENABLE, mdp_intr_mask);
spin_unlock_irqrestore(&mdp_spin_lock, flag);
wait_for_completion_killable(&atv_pipe->comp);
mdp_disable_irq(MDP_OVERLAY1_TERM);
mdp4_overlay_mdp_perf_upd(mfd, 0);
mdp4_stat.kickoff_atv++;
mutex_unlock(&mfd->dma->ov_mutex);
}
static void mdp4_overlay_dtv_alloc_pipe(struct msm_fb_data_type *mfd,
int32 ptype, struct vsycn_ctrl *vctrl)
{
int ret = 0;
struct fb_info *fbi = mfd->fbi;
struct mdp4_overlay_pipe *pipe;
if (vctrl->base_pipe != NULL)
return;
pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER1);
if (pipe == NULL) {
pr_err("%s: pipe_alloc failed\n", __func__);
return;
}
pipe->pipe_used++;
pipe->mixer_stage = MDP4_MIXER_STAGE_BASE;
pipe->mixer_num = MDP4_MIXER1;
if (ptype == OVERLAY_TYPE_BF) {
/* LSP_BORDER_COLOR */
MDP_OUTP(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x5004,
((0x0 & 0xFFF) << 16) | /* 12-bit B */
(0x0 & 0xFFF)); /* 12-bit G */
/* MSP_BORDER_COLOR */
MDP_OUTP(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x5008,
(0x0 & 0xFFF)); /* 12-bit R */
pipe->src_format = MDP_ARGB_8888;
} else {
switch (mfd->ibuf.bpp) {
case 2:
pipe->src_format = MDP_RGB_565;
break;
case 3:
pipe->src_format = MDP_RGB_888;
break;
case 4:
default:
if (hdmi_prim_display)
pipe->src_format = MSMFB_DEFAULT_TYPE;
else
pipe->src_format = MDP_ARGB_8888;
break;
}
}
pipe->src_height = fbi->var.yres;
pipe->src_width = fbi->var.xres;
pipe->src_h = fbi->var.yres;
pipe->src_w = fbi->var.xres;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->src_y = 0;
pipe->src_x = 0;
pipe->dst_h = fbi->var.yres;
pipe->dst_w = fbi->var.xres;
pipe->srcp0_ystride = fbi->fix.line_length;
mdp4_overlay_mdp_pipe_req(pipe, mfd);
mdp4_calc_blt_mdp_bw(mfd, pipe);
mdp4_overlay_mdp_perf_req(mfd);
mdp4_overlay_mdp_perf_upd(mfd, 1);
ret = mdp4_overlay_format2pipe(pipe);
if (ret < 0)
pr_warn("%s: format2type failed\n", __func__);
mdp4_overlay_dmae_xy(pipe); /* dma_e */
mdp4_overlayproc_cfg(pipe);
if (pipe->pipe_type == OVERLAY_TYPE_RGB) {
pipe->srcp0_addr = (uint32) mfd->ibuf.buf;
mdp4_overlay_rgb_setup(pipe);
}
mdp4_overlay_reg_flush(pipe, 1);
mdp4_mixer_stage_up(pipe, 0);
mdp4_mixer_stage_commit(pipe->mixer_num);
vctrl->base_pipe = pipe; /* keep it */
}
