void mdss_dsi_error(struct mdss_dsi_ctrl_pdata *ctrl)
{
/* disable dsi error interrupt */
mdss_dsi_err_intr_ctrl(ctrl, DSI_INTR_ERROR_MASK, 0);
/* DSI_ERR_INT_MASK0 */
mdss_dsi_clk_status(ctrl); /* Mask0, 0x10000000 */
mdss_dsi_fifo_status(ctrl); /* mask0, 0x133d00 */
mdss_dsi_ack_err_status(ctrl); /* mask0, 0x01f */
mdss_dsi_timeout_status(ctrl); /* mask0, 0x0e0 */
mdss_dsi_status(ctrl); /* mask0, 0xc0100 */
mdss_dsi_dln0_phy_err(ctrl); /* mask0, 0x3e00000 */
dsi_send_events(ctrl, DSI_EV_MDP_BUSY_RELEASE);
#if defined(CONFIG_F_SKYDISP_EF63_SS) //ejkim77_debug dump
#ifdef F_WA_WATCHDOG_DURING_BOOTUP
if(ctrl->octa_blck_set && !ctrl->manufacture_id)
#endif
{
dumpreg();
BUG_ON(1);
}
#endif
}
void mdss_dsi_error(unsigned char *dsi_base)
{
/* DSI_ERR_INT_MASK0 */
mdss_dsi_ack_err_status(dsi_base); /* mask0, 0x01f */
mdss_dsi_timeout_status(dsi_base); /* mask0, 0x0e0 */
mdss_dsi_fifo_status(dsi_base); /* mask0, 0x133d00 */
mdss_dsi_status(dsi_base); /* mask0, 0xc0100 */
mdss_dsi_dln0_phy_err(dsi_base); /* mask0, 0x3e00000 */
}
void mdss_dsi_error(struct mdss_dsi_ctrl_pdata *ctrl)
{
unsigned char *base;
base = ctrl->ctrl_base;
/* DSI_ERR_INT_MASK0 */
mdss_dsi_ack_err_status(base); /* mask0, 0x01f */
mdss_dsi_timeout_status(base); /* mask0, 0x0e0 */
mdss_dsi_fifo_status(base); /* mask0, 0x133d00 */
mdss_dsi_status(base); /* mask0, 0xc0100 */
mdss_dsi_dln0_phy_err(base); /* mask0, 0x3e00000 */
}
void mdss_dsi_error(struct mdss_dsi_ctrl_pdata *ctrl)
{
/* disable dsi error interrupt */
mdss_dsi_err_intr_ctrl(ctrl, DSI_INTR_ERROR_MASK, 0);
/* DSI_ERR_INT_MASK0 */
mdss_dsi_clk_status(ctrl); /* Mask0, 0x10000000 */
mdss_dsi_fifo_status(ctrl); /* mask0, 0x133d00 */
mdss_dsi_ack_err_status(ctrl); /* mask0, 0x01f */
mdss_dsi_timeout_status(ctrl); /* mask0, 0x0e0 */
mdss_dsi_status(ctrl); /* mask0, 0xc0100 */
mdss_dsi_dln0_phy_err(ctrl); /* mask0, 0x3e00000 */
dsi_send_events(ctrl, DSI_EV_MDP_BUSY_RELEASE);
}
void mdss_dsi_error(struct mdss_dsi_ctrl_pdata *ctrl)
{
mdss_dsi_err_intr_ctrl(ctrl, DSI_INTR_ERROR_MASK, 0);
mdss_dsi_clk_status(ctrl);
mdss_dsi_fifo_status(ctrl);
mdss_dsi_ack_err_status(ctrl);
mdss_dsi_timeout_status(ctrl);
mdss_dsi_status(ctrl);
mdss_dsi_dln0_phy_err(ctrl);
dsi_send_events(ctrl, DSI_EV_MDP_BUSY_RELEASE);
}
/**
* mdss_dsi_ulps_config() - Program DSI lanes to enter/exit ULPS mode
* @ctrl: pointer to DSI controller structure
* @enable: 1 to enter ULPS, 0 to exit ULPS
*
* This function executes the necessary programming sequence to enter/exit
* DSI Ultra-Low Power State (ULPS). This function assumes that the link and
* bus clocks are already on.
*/
static int mdss_dsi_ulps_config(struct mdss_dsi_ctrl_pdata *ctrl,
int enable)
{
int ret = 0;
struct mdss_panel_data *pdata = NULL;
struct mdss_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 lane_status = 0;
u32 active_lanes = 0;
if (!ctrl) {
pr_err("%s: invalid input\n", __func__);
return -EINVAL;
}
pdata = &ctrl->panel_data;
if (!pdata) {
pr_err("%s: Invalid panel data\n", __func__);
return -EINVAL;
}
pinfo = &pdata->panel_info;
mipi = &pinfo->mipi;
if (!mdss_dsi_ulps_feature_enabled(pdata) &&
!pinfo->ulps_suspend_enabled) {
pr_debug("%s: ULPS feature not supported. enable=%d\n",
__func__, enable);
return -ENOTSUPP;
}
/*
* No need to enter ULPS when transitioning from splash screen to
* boot animation since it is expected that the clocks would be turned
* right back on.
*/
if (pinfo->cont_splash_enabled) {
pr_debug("%s: skip ULPS config with splash screen enabled\n",
__func__);
return 0;
}
/* clock lane will always be programmed for ulps */
active_lanes = BIT(4);
/*
* make a note of all active data lanes for which ulps entry/exit
* is needed
*/
if (mipi->data_lane0)
active_lanes |= BIT(0);
if (mipi->data_lane1)
active_lanes |= BIT(1);
if (mipi->data_lane2)
active_lanes |= BIT(2);
if (mipi->data_lane3)
active_lanes |= BIT(3);
pr_debug("%s: configuring ulps (%s) for ctrl%d, active lanes=0x%08x\n",
__func__, (enable ? "on" : "off"), ctrl->ndx,
active_lanes);
if (enable && !ctrl->ulps) {
/*
* ULPS Entry Request.
* Wait for a short duration to ensure that the lanes
* enter ULP state.
*/
MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes);
usleep(100);
/* Check to make sure that all active data lanes are in ULPS */
lane_status = MIPI_INP(ctrl->ctrl_base + 0xA8);
if (lane_status & (active_lanes << 8)) {
pr_err("%s: ULPS entry req failed for ctrl%d. Lane status=0x%08x\n",
__func__, ctrl->ndx, lane_status);
ret = -EINVAL;
goto error;
}
ctrl->ulps = true;
} else if (!enable && ctrl->ulps) {
/*
* Clear out any phy errors prior to exiting ULPS
* This fixes certain instances where phy does not exit
* ULPS cleanly.
*/
mdss_dsi_dln0_phy_err(ctrl);
/*
* ULPS Exit Request
* Hardware requirement is to wait for at least 1ms
*/
MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes << 8);
usleep(1000);
/*
* Sometimes when exiting ULPS, it is possible that some DSI
* lanes are not in the stop state which could lead to DSI
* commands not going through. To avoid this, force the lanes
* to be in stop state.
*/
MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes << 16);
MIPI_OUTP(ctrl->ctrl_base + 0x0AC, 0x0);
/*
* Wait for a short duration before enabling
* data transmission
*/
usleep(100);
lane_status = MIPI_INP(ctrl->ctrl_base + 0xA8);
ctrl->ulps = false;
} else {
pr_debug("%s: No change requested: %s -> %s\n", __func__,
ctrl->ulps ? "enabled" : "disabled",
enable ? "enabled" : "disabled");
}
pr_debug("%s: DSI lane status = 0x%08x. Ulps %s\n", __func__,
lane_status, enable ? "enabled" : "disabled");
error:
return ret;
}
/**
* mdss_dsi_ulps_config() - Program DSI lanes to enter/exit ULPS mode
* @ctrl: pointer to DSI controller structure
* @enable: 1 to enter ULPS, 0 to exit ULPS
*
* This function executes the necessary programming sequence to enter/exit
* DSI Ultra-Low Power State (ULPS). This function assumes that the link and
* bus clocks are already on.
*/
static int mdss_dsi_ulps_config(struct mdss_dsi_ctrl_pdata *ctrl,
int enable)
{
int ret = 0;
struct mdss_panel_data *pdata = NULL;
struct mdss_panel_info *pinfo;
struct mipi_panel_info *mipi;
u32 lane_status = 0;
u32 active_lanes = 0;
if (!ctrl) {
pr_err("%s: invalid input\n", __func__);
return -EINVAL;
}
pdata = &ctrl->panel_data;
if (!pdata) {
pr_err("%s: Invalid panel data\n", __func__);
return -EINVAL;
}
pinfo = &pdata->panel_info;
mipi = &pinfo->mipi;
if (!mdss_dsi_is_ulps_req_valid(ctrl, enable)) {
pr_debug("%s: skiping ULPS config for ctrl%d, enable=%d\n",
__func__, ctrl->ndx, enable);
return 0;
}
/* clock lane will always be programmed for ulps */
active_lanes = BIT(4);
/*
* make a note of all active data lanes for which ulps entry/exit
* is needed
*/
if (mipi->data_lane0)
active_lanes |= BIT(0);
if (mipi->data_lane1)
active_lanes |= BIT(1);
if (mipi->data_lane2)
active_lanes |= BIT(2);
if (mipi->data_lane3)
active_lanes |= BIT(3);
pr_debug("%s: configuring ulps (%s) for ctrl%d, active lanes=0x%08x,clamps=%s\n",
__func__, (enable ? "on" : "off"), ctrl->ndx,
active_lanes, ctrl->mmss_clamp ? "enabled" : "disabled");
if (enable && !ctrl->ulps) {
/*
* Ensure that the lanes are idle prior to placing a ULPS entry
* request. This is needed to ensure that there is no overlap
* between any HS or LP commands being sent out on the lane and
* a potential ULPS entry request.
*
* This check needs to be avoided when we are resuming from idle
* power collapse and just restoring the controller state to
* ULPS with the clamps still in place.
*/
if (!ctrl->mmss_clamp) {
ret = mdss_dsi_wait_for_lane_idle(ctrl);
if (ret) {
pr_warn("%s: lanes not idle, skip ulps\n",
__func__);
ret = 0;
goto error;
}
}
/*
* ULPS Entry Request.
* Wait for a short duration to ensure that the lanes
* enter ULP state.
*/
MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes);
usleep(100);
/* Check to make sure that all active data lanes are in ULPS */
lane_status = MIPI_INP(ctrl->ctrl_base + 0xA8);
if (lane_status & (active_lanes << 8)) {
pr_err("%s: ULPS entry req failed for ctrl%d. Lane status=0x%08x\n",
__func__, ctrl->ndx, lane_status);
ret = -EINVAL;
goto error;
}
ctrl->ulps = true;
} else if (!enable && ctrl->ulps) {
/*
* Clear out any phy errors prior to exiting ULPS
* This fixes certain instances where phy does not exit
* ULPS cleanly.
*/
mdss_dsi_dln0_phy_err(ctrl);
/*
* ULPS Exit Request
* Hardware requirement is to wait for at least 1ms
*/
MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes << 8);
usleep(1000);
/*
* Sometimes when exiting ULPS, it is possible that some DSI
* lanes are not in the stop state which could lead to DSI
* commands not going through. To avoid this, force the lanes
* to be in stop state.
*/
MIPI_OUTP(ctrl->ctrl_base + 0x0AC, active_lanes << 16);
MIPI_OUTP(ctrl->ctrl_base + 0x0AC, 0x0);
/*
* Wait for a short duration before enabling
* data transmission
*/
usleep(100);
lane_status = MIPI_INP(ctrl->ctrl_base + 0xA8);
ctrl->ulps = false;
} else {
pr_debug("%s: No change requested: %s -> %s\n", __func__,
ctrl->ulps ? "enabled" : "disabled",
enable ? "enabled" : "disabled");
}
pr_debug("%s: DSI lane status = 0x%08x. Ulps %s\n", __func__,
lane_status, enable ? "enabled" : "disabled");
error:
return ret;
}
