static int mdss_panel_parse_dt(struct platform_device *pdev, struct mdss_panel_common_pdata *panel_data) { struct device_node *np = pdev->dev.of_node; u32 res[6], tmp; u32 fbc_res[7]; int rc, i, len; const char *data; static const char *bl_ctrl_type, *pdest; bool fbc_enabled = false; rc = of_property_read_u32_array(np, "qcom,mdss-pan-res", res, 2); if (rc) { pr_err("%s:%d, panel resolution not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.xres = (!rc ? res[0] : 640); panel_data->panel_info.yres = (!rc ? res[1] : 480); rc = of_property_read_u32(np, "qcom,mdss-pan-id", &tmp); if (!rc) mdss_panel_id = tmp; pr_info("%s: Panel ID = %d\n", __func__, mdss_panel_id); mdss_panel_flip_ud = of_property_read_bool(np, "qcom,mdss-pan-flip-ud"); if (mdss_panel_flip_ud) pr_info("%s: Panel FLIP UD\n", __func__); rc = of_property_read_u32_array(np, "qcom,mdss-pan-active-res", res, 2); if (rc == 0) { panel_data->panel_info.lcdc.xres_pad = panel_data->panel_info.xres - res[0]; panel_data->panel_info.lcdc.yres_pad = panel_data->panel_info.yres - res[1]; } rc = of_property_read_u32(np, "qcom,mdss-pan-bpp", &tmp); if (rc) { pr_err("%s:%d, panel bpp not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.bpp = (!rc ? tmp : 24); rc = of_property_read_u32(np, "qcom,mdss-pan-width", &tmp); if (rc) pr_warn("%s:%d, panel width not specified\n", __func__, __LINE__); panel_data->panel_info.width = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-height", &tmp); if (rc) pr_warn("%s:%d, panel height not specified\n", __func__, __LINE__); panel_data->panel_info.height = (!rc ? tmp : 0); pdest = of_get_property(pdev->dev.of_node, "qcom,mdss-pan-dest", NULL); if (strlen(pdest) != 9) { pr_err("%s: Unknown pdest specified\n", __func__); return -EINVAL; } if (!strncmp(pdest, "display_1", 9)) panel_data->panel_info.pdest = DISPLAY_1; else if (!strncmp(pdest, "display_2", 9)) panel_data->panel_info.pdest = DISPLAY_2; else { pr_debug("%s: pdest not specified. Set Default\n", __func__); panel_data->panel_info.pdest = DISPLAY_1; } rc = of_property_read_u32_array(np, "qcom,mdss-pan-porch-values", res, 6); panel_data->panel_info.lcdc.h_back_porch = (!rc ? res[0] : 6); panel_data->panel_info.lcdc.h_pulse_width = (!rc ? res[1] : 2); panel_data->panel_info.lcdc.h_front_porch = (!rc ? res[2] : 6); panel_data->panel_info.lcdc.v_back_porch = (!rc ? res[3] : 6); panel_data->panel_info.lcdc.v_pulse_width = (!rc ? res[4] : 2); panel_data->panel_info.lcdc.v_front_porch = (!rc ? res[5] : 6); rc = of_property_read_u32(np, "qcom,mdss-pan-underflow-clr", &tmp); panel_data->panel_info.lcdc.underflow_clr = (!rc ? tmp : 0xff); bl_ctrl_type = of_get_property(pdev->dev.of_node, "qcom,mdss-pan-bl-ctrl", NULL); if ((bl_ctrl_type) && (!strncmp(bl_ctrl_type, "bl_ctrl_wled", 12))) { led_trigger_register_simple("bkl-trigger", &bl_led_trigger); pr_debug("%s: SUCCESS-> WLED TRIGGER register\n", __func__); panel_data->panel_info.bklt_ctrl = BL_WLED; } else if (!strncmp(bl_ctrl_type, "bl_ctrl_pwm", 11)) { panel_data->panel_info.bklt_ctrl = BL_PWM; rc = of_property_read_u32(np, "qcom,pwm-period", &tmp); if (rc) { pr_err("%s:%d, Error, panel pwm_period\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.pwm_period = tmp; rc = of_property_read_u32(np, "qcom,pwm-lpg-channel", &tmp); if (rc) { pr_err("%s:%d, Error, dsi lpg channel\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.pwm_lpg_chan = tmp; tmp = of_get_named_gpio(np, "qcom,pwm-pmic-gpio", 0); panel_data->panel_info.pwm_pmic_gpio = tmp; } else if (!strncmp(bl_ctrl_type, "bl_ctrl_dcs", 11)) { panel_data->panel_info.bklt_ctrl = BL_DCS_CMD; } else { pr_debug("%s: Unknown backlight control\n", __func__); panel_data->panel_info.bklt_ctrl = UNKNOWN_CTRL; } rc = of_property_read_u32_array(np, "qcom,mdss-pan-bl-levels", res, 2); panel_data->panel_info.bl_min = (!rc ? res[0] : 0); panel_data->panel_info.bl_max = (!rc ? res[1] : 255); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mode", &tmp); panel_data->panel_info.mipi.mode = (!rc ? tmp : DSI_VIDEO_MODE); rc = of_property_read_u32(np, "qcom,mdss-vsync-enable", &tmp); panel_data->panel_info.mipi.vsync_enable = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-hw-vsync-mode", &tmp); panel_data->panel_info.mipi.hw_vsync_mode = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-h-pulse-mode", &tmp); panel_data->panel_info.mipi.pulse_mode_hsa_he = (!rc ? tmp : false); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-h-power-stop", res, 3); panel_data->panel_info.mipi.hbp_power_stop = (!rc ? res[0] : false); panel_data->panel_info.mipi.hsa_power_stop = (!rc ? res[1] : false); panel_data->panel_info.mipi.hfp_power_stop = (!rc ? res[2] : false); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-bllp-power-stop", res, 2); panel_data->panel_info.mipi.bllp_power_stop = (!rc ? res[0] : false); panel_data->panel_info.mipi.eof_bllp_power_stop = (!rc ? res[1] : false); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-traffic-mode", &tmp); panel_data->panel_info.mipi.traffic_mode = (!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE); rc = of_property_read_u32(np, "qcom,mdss-pan-insert-dcs-cmd", &tmp); panel_data->panel_info.mipi.insert_dcs_cmd = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-pan-wr-mem-continue", &tmp); panel_data->panel_info.mipi.wr_mem_continue = (!rc ? tmp : 0x3c); rc = of_property_read_u32(np, "qcom,mdss-pan-wr-mem-start", &tmp); panel_data->panel_info.mipi.wr_mem_start = (!rc ? tmp : 0x2c); rc = of_property_read_u32(np, "qcom,mdss-pan-te-sel", &tmp); panel_data->panel_info.mipi.te_sel = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dst-format", &tmp); panel_data->panel_info.mipi.dst_format = (!rc ? tmp : DSI_VIDEO_DST_FORMAT_RGB888); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-vc", &tmp); panel_data->panel_info.mipi.vc = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-rgb-swap", &tmp); panel_data->panel_info.mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-data-lanes", res, 4); panel_data->panel_info.mipi.data_lane0 = (!rc ? res[0] : true); panel_data->panel_info.mipi.data_lane1 = (!rc ? res[1] : false); panel_data->panel_info.mipi.data_lane2 = (!rc ? res[2] : false); panel_data->panel_info.mipi.data_lane3 = (!rc ? res[3] : false); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dlane-swap", &tmp); panel_data->panel_info.mipi.dlane_swap = (!rc ? tmp : 0); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-t-clk", res, 2); panel_data->panel_info.mipi.t_clk_pre = (!rc ? res[0] : 0x24); panel_data->panel_info.mipi.t_clk_post = (!rc ? res[1] : 0x03); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-stream", &tmp); panel_data->panel_info.mipi.stream = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mdp-tr", &tmp); panel_data->panel_info.mipi.mdp_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (panel_data->panel_info.mipi.mdp_trigger > 6) { pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger", __func__, __LINE__); panel_data->panel_info.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dma-tr", &tmp); panel_data->panel_info.mipi.dma_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (panel_data->panel_info.mipi.dma_trigger > 6) { pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger", __func__, __LINE__); panel_data->panel_info.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-frame-rate", &tmp); panel_data->panel_info.mipi.frame_rate = (!rc ? tmp : 60); rc = of_property_read_u32(np, "qcom,mdss-pan-clk-rate", &tmp); panel_data->panel_info.clk_rate = (!rc ? tmp : 0); data = of_get_property(np, "qcom,panel-phy-regulatorSettings", &len); if ((!data) || (len != 7)) { pr_err("%s:%d, Unable to read Phy regulator settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.regulator[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-timingSettings", &len); if ((!data) || (len != 12)) { pr_err("%s:%d, Unable to read Phy timing settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.timing[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-strengthCtrl", &len); if ((!data) || (len != 2)) { pr_err("%s:%d, Unable to read Phy Strength ctrl settings", __func__, __LINE__); goto error; } phy_params.strength[0] = data[0]; phy_params.strength[1] = data[1]; data = of_get_property(np, "qcom,panel-phy-bistCtrl", &len); if ((!data) || (len != 6)) { pr_err("%s:%d, Unable to read Phy Bist Ctrl settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.bistCtrl[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-laneConfig", &len); if ((!data) || (len != 45)) { pr_err("%s:%d, Unable to read Phy lane configure settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.laneCfg[i] = data[i]; panel_data->panel_info.mipi.dsi_phy_db = &phy_params; fbc_enabled = of_property_read_bool(np, "qcom,fbc-enabled"); if (fbc_enabled) { pr_debug("%s:%d FBC panel enabled.\n", __func__, __LINE__); panel_data->panel_info.fbc.enabled = 1; rc = of_property_read_u32_array(np, "qcom,fbc-mode", fbc_res, 7); panel_data->panel_info.fbc.target_bpp = (!rc ? fbc_res[0] : panel_data->panel_info.bpp); panel_data->panel_info.fbc.comp_mode = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.qerr_enable = (!rc ? fbc_res[2] : 0); panel_data->panel_info.fbc.cd_bias = (!rc ? fbc_res[3] : 0); panel_data->panel_info.fbc.pat_enable = (!rc ? fbc_res[4] : 0); panel_data->panel_info.fbc.vlc_enable = (!rc ? fbc_res[5] : 0); panel_data->panel_info.fbc.bflc_enable = (!rc ? fbc_res[6] : 0); rc = of_property_read_u32_array(np, "qcom,fbc-budget-ctl", fbc_res, 3); panel_data->panel_info.fbc.line_x_budget = (!rc ? fbc_res[0] : 0); panel_data->panel_info.fbc.block_x_budget = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.block_budget = (!rc ? fbc_res[2] : 0); rc = of_property_read_u32_array(np, "qcom,fbc-lossy-mode", fbc_res, 4); panel_data->panel_info.fbc.lossless_mode_thd = (!rc ? fbc_res[0] : 0); panel_data->panel_info.fbc.lossy_mode_thd = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.lossy_rgb_thd = (!rc ? fbc_res[2] : 0); panel_data->panel_info.fbc.lossy_mode_idx = (!rc ? fbc_res[3] : 0); } else { pr_debug("%s:%d Panel does not support FBC.\n", __func__, __LINE__); panel_data->panel_info.fbc.enabled = 0; panel_data->panel_info.fbc.target_bpp = panel_data->panel_info.bpp; } mdss_dsi_parse_dcs_cmds(np, &panel_data->on_cmds, "qcom,panel-on-cmds", "qcom,on-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &panel_data->off_cmds, "qcom,panel-off-cmds", "qcom,off-cmds-dsi-state"); return 0; error: return -EINVAL; }
static int mdss_panel_parse_dt(struct device_node *np, struct mdss_dsi_ctrl_pdata *ctrl_pdata) { u32 res[6], tmp; int rc, i, len; const char *data; static const char *bl_ctrl_type, *pdest; struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info); rc = of_property_read_u32_array(np, "qcom,mdss-pan-res", res, 2); if (rc) { pr_err("%s:%d, panel resolution not specified\n", __func__, __LINE__); return -EINVAL; } pinfo->xres = (!rc ? res[0] : 640); pinfo->yres = (!rc ? res[1] : 480); rc = of_property_read_u32_array(np, "qcom,mdss-pan-active-res", res, 2); if (rc == 0) { pinfo->lcdc.xres_pad = pinfo->xres - res[0]; pinfo->lcdc.yres_pad = pinfo->yres - res[1]; } rc = of_property_read_u32_array(np, "qcom,mdss-pan-physical-dimension", res, 2); pinfo->physical_width = (!rc ? res[0] : -1); pinfo->physical_height = (!rc ? res[1] : -1); pr_debug("Panel Physical Width=%d, Height=%d\n", pinfo->physical_width, pinfo->physical_height); rc = of_property_read_u32(np, "qcom,mdss-pan-bpp", &tmp); if (rc) { pr_err("%s:%d, panel bpp not specified\n", __func__, __LINE__); return -EINVAL; } pinfo->bpp = (!rc ? tmp : 24); pdest = of_get_property(np, "qcom,mdss-pan-dest", NULL); if (strlen(pdest) != 9) { pr_err("%s: Unknown pdest specified\n", __func__); return -EINVAL; } if (!strncmp(pdest, "display_1", 9)) pinfo->pdest = DISPLAY_1; else if (!strncmp(pdest, "display_2", 9)) pinfo->pdest = DISPLAY_2; else { pr_debug("%s: pdest not specified. Set Default\n", __func__); pinfo->pdest = DISPLAY_1; } rc = of_property_read_u32_array(np, "qcom,mdss-pan-porch-values", res, 6); pinfo->lcdc.h_back_porch = (!rc ? res[0] : 6); pinfo->lcdc.h_pulse_width = (!rc ? res[1] : 2); pinfo->lcdc.h_front_porch = (!rc ? res[2] : 6); pinfo->lcdc.v_back_porch = (!rc ? res[3] : 6); pinfo->lcdc.v_pulse_width = (!rc ? res[4] : 2); pinfo->lcdc.v_front_porch = (!rc ? res[5] : 6); rc = of_property_read_u32(np, "qcom,mdss-pan-underflow-clr", &tmp); pinfo->lcdc.underflow_clr = (!rc ? tmp : 0xff); bl_ctrl_type = of_get_property(np, "qcom,mdss-pan-bl-ctrl", NULL); if ((bl_ctrl_type) && (!strncmp(bl_ctrl_type, "bl_ctrl_wled", 12))) { led_trigger_register_simple("bkl-trigger", &bl_led_trigger); pr_err("%s: SUCCESS-> WLED TRIGGER register\n", __func__); pinfo->bklt_ctrl = BL_WLED; } else if (!strncmp(bl_ctrl_type, "bl_ctrl_pwm", 11)) { ctrl_pdata->bklt_ctrl = BL_PWM; rc = of_property_read_u32(np, "qcom,pwm-period", &tmp); if (rc) { pr_err("%s:%d, Error, panel pwm_period\n", __func__, __LINE__); return -EINVAL; } ctrl_pdata->pwm_period = tmp; rc = of_property_read_u32(np, "qcom,pwm-lpg-channel", &tmp); if (rc) { pr_err("%s:%d, Error, dsi lpg channel\n", __func__, __LINE__); return -EINVAL; } ctrl_pdata->pwm_lpg_chan = tmp; tmp = of_get_named_gpio(np, "qcom,pwm-pmic-gpio", 0); ctrl_pdata->pwm_pmic_gpio = tmp; pr_info("%s: pwm_pmic_gpio=%d\n",__func__, ctrl_pdata->pwm_pmic_gpio); } else if (!strncmp(bl_ctrl_type, "bl_ctrl_dcs", 11)) { pr_info("%s: BL DCS Control \n",__func__); pinfo->bklt_ctrl = BL_DCS_CMD; } else { pr_err("%s: Unknown backlight control\n", __func__); pinfo->bklt_ctrl = UNKNOWN_CTRL; } rc = of_property_read_u32(np, "qcom,mdss-brightness-max-level", &tmp); pinfo->brightness_max = (!rc ? tmp : MDSS_MAX_BL_BRIGHTNESS); rc = of_property_read_u32_array(np, "qcom,mdss-pan-bl-levels", res, 2); pinfo->bl_min = (!rc ? res[0] : 0); pinfo->bl_max = (!rc ? res[1] : 255); ctrl_pdata->bklt_max = pinfo->bl_max; rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mode", &tmp); pinfo->mipi.mode = (!rc ? tmp : DSI_VIDEO_MODE); rc = of_property_read_u32(np, "qcom,mdss-vsync-enable", &tmp); pinfo->mipi.vsync_enable = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-hw-vsync-mode", &tmp); pinfo->mipi.hw_vsync_mode = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-h-pulse-mode", &tmp); pinfo->mipi.pulse_mode_hsa_he = (!rc ? tmp : false); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-h-power-stop", res, 3); pinfo->mipi.hbp_power_stop = (!rc ? res[0] : false); pinfo->mipi.hsa_power_stop = (!rc ? res[1] : false); pinfo->mipi.hfp_power_stop = (!rc ? res[2] : false); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-bllp-power-stop", res, 2); pinfo->mipi.bllp_power_stop = (!rc ? res[0] : false); pinfo->mipi.eof_bllp_power_stop = (!rc ? res[1] : false); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-traffic-mode", &tmp); pinfo->mipi.traffic_mode = (!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE); rc = of_property_read_u32(np, "qcom,mdss-pan-insert-dcs-cmd", &tmp); pinfo->mipi.insert_dcs_cmd = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-pan-wr-mem-continue", &tmp); pinfo->mipi.wr_mem_continue = (!rc ? tmp : 0x3c); rc = of_property_read_u32(np, "qcom,mdss-pan-wr-mem-start", &tmp); pinfo->mipi.wr_mem_start = (!rc ? tmp : 0x2c); rc = of_property_read_u32(np, "qcom,mdss-pan-te-sel", &tmp); pinfo->mipi.te_sel = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dst-format", &tmp); pinfo->mipi.dst_format = (!rc ? tmp : DSI_VIDEO_DST_FORMAT_RGB888); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-vc", &tmp); pinfo->mipi.vc = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-rgb-swap", &tmp); pinfo->mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB); rc = of_property_read_u32(np, "qcom,mdss-force-clk-lane-hs", &tmp); pinfo->mipi.force_clk_lane_hs = (!rc ? tmp : 0); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-data-lanes", res, 4); pinfo->mipi.data_lane0 = (!rc ? res[0] : true); pinfo->mipi.data_lane1 = (!rc ? res[1] : false); pinfo->mipi.data_lane2 = (!rc ? res[2] : false); pinfo->mipi.data_lane3 = (!rc ? res[3] : false); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dlane-swap", &tmp); pinfo->mipi.dlane_swap = (!rc ? tmp : 0); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-t-clk", res, 2); pinfo->mipi.t_clk_pre = (!rc ? res[0] : 0x24); pinfo->mipi.t_clk_post = (!rc ? res[1] : 0x03); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-stream", &tmp); pinfo->mipi.stream = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mdp-tr", &tmp); pinfo->mipi.mdp_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (pinfo->mipi.mdp_trigger > 6) { pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger", __func__, __LINE__); pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dma-tr", &tmp); pinfo->mipi.dma_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (pinfo->mipi.dma_trigger > 6) { pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger", __func__, __LINE__); pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-frame-rate", &tmp); pinfo->mipi.frame_rate = (!rc ? tmp : 60); rc = of_property_read_u32(np, "qcom,mdss-pan-clk-rate", &tmp); pinfo->clk_rate = (!rc ? tmp : 0); data = of_get_property(np, "qcom,panel-phy-regulatorSettings", &len); if ((!data) || (len != 7)) { pr_err("%s:%d, Unable to read Phy regulator settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.regulator[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-timingSettings", &len); if ((!data) || (len != 12)) { pr_err("%s:%d, Unable to read Phy timing settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.timing[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-strengthCtrl", &len); if ((!data) || (len != 2)) { pr_err("%s:%d, Unable to read Phy Strength ctrl settings", __func__, __LINE__); goto error; } phy_params.strength[0] = data[0]; phy_params.strength[1] = data[1]; data = of_get_property(np, "qcom,panel-phy-bistCtrl", &len); if ((!data) || (len != 6)) { pr_err("%s:%d, Unable to read Phy Bist Ctrl settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.bistctrl[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-laneConfig", &len); if ((!data) || (len != 45)) { pr_err("%s:%d, Unable to read Phy lane configure settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.lanecfg[i] = data[i]; pinfo->mipi.dsi_phy_db = phy_params; mdss_dsi_parse_fbc_params(np, pinfo); mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds, "qcom,panel-on-cmds", "qcom,on-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->off_cmds, "qcom,panel-off-cmds", "qcom,off-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->ce_on_cmds, "samsung,panel-ce-on-cmds", "qcom,on-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->ce_off_cmds, "samsung,panel-ce-off-cmds", "qcom,off-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->cabc_on_cmds, "samsung,panel-cabc-on-cmds", "qcom,on-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->cabc_off_cmds, "samsung,panel-cabc-off-cmds", "qcom,off-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->cabc_tune_cmds, "samsung,panel-cabc-tune-cmds", "qcom,off-cmds-dsi-state"); return 0; error: return -EINVAL; }
static int mdss_panel_parse_dt(struct device_node *np, struct mdss_dsi_ctrl_pdata *ctrl_pdata) { u32 tmp; int rc, i, len; const char *data; static const char *pdest; struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info); rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-width", &tmp); if (rc) { pr_err("%s:%d, panel width not specified\n", __func__, __LINE__); return -EINVAL; } pinfo->xres = (!rc ? tmp : 640); rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-height", &tmp); if (rc) { pr_err("%s:%d, panel height not specified\n", __func__, __LINE__); return -EINVAL; } pinfo->yres = (!rc ? tmp : 480); rc = of_property_read_u32(np, "qcom,mdss-pan-physical-width-dimension", &tmp); pinfo->physical_width = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-physical-height-dimension", &tmp); pinfo->physical_height = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-left-border", &tmp); pinfo->lcdc.xres_pad = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-right-border", &tmp); if (!rc) pinfo->lcdc.xres_pad += tmp; rc = of_property_read_u32(np, "qcom,mdss-dsi-v-top-border", &tmp); pinfo->lcdc.yres_pad = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-v-bottom-border", &tmp); if (!rc) pinfo->lcdc.yres_pad += tmp; rc = of_property_read_u32(np, "qcom,mdss-dsi-bpp", &tmp); if (rc) { pr_err("%s:%d, bpp not specified\n", __func__, __LINE__); return -EINVAL; } pinfo->bpp = (!rc ? tmp : 24); pinfo->mipi.mode = DSI_VIDEO_MODE; data = of_get_property(np, "qcom,mdss-dsi-panel-type", NULL); if (data && !strncmp(data, "dsi_cmd_mode", 12)) pinfo->mipi.mode = DSI_CMD_MODE; rc = of_property_read_u32(np, "qcom,mdss-dsi-pixel-packing", &tmp); tmp = (!rc ? tmp : 0); rc = mdss_panel_dt_get_dst_fmt(pinfo->bpp, pinfo->mipi.mode, tmp, &(pinfo->mipi.dst_format)); if (rc) { pr_debug("%s: problem determining dst format. Set Default\n", __func__); pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; } pdest = of_get_property(np, "qcom,mdss-dsi-panel-destination", NULL); if (strlen(pdest) != 9) { pr_err("%s: Unknown pdest specified\n", __func__); return -EINVAL; } if (!strncmp(pdest, "display_1", 9)) pinfo->pdest = DISPLAY_1; else if (!strncmp(pdest, "display_2", 9)) pinfo->pdest = DISPLAY_2; else { pr_debug("%s: pdest not specified. Set Default\n", __func__); pinfo->pdest = DISPLAY_1; } rc = of_property_read_u32(np, "qcom,mdss-dsi-h-front-porch", &tmp); pinfo->lcdc.h_front_porch = (!rc ? tmp : 6); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-back-porch", &tmp); pinfo->lcdc.h_back_porch = (!rc ? tmp : 6); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-pulse-width", &tmp); pinfo->lcdc.h_pulse_width = (!rc ? tmp : 2); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-sync-skew", &tmp); pinfo->lcdc.hsync_skew = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-v-back-porch", &tmp); pinfo->lcdc.v_back_porch = (!rc ? tmp : 6); rc = of_property_read_u32(np, "qcom,mdss-dsi-v-front-porch", &tmp); pinfo->lcdc.v_front_porch = (!rc ? tmp : 6); rc = of_property_read_u32(np, "qcom,mdss-dsi-v-pulse-width", &tmp); pinfo->lcdc.v_pulse_width = (!rc ? tmp : 2); rc = of_property_read_u32(np, "qcom,mdss-dsi-underflow-color", &tmp); pinfo->lcdc.underflow_clr = (!rc ? tmp : 0xff); rc = of_property_read_u32(np, "qcom,mdss-dsi-border-color", &tmp); pinfo->lcdc.border_clr = (!rc ? tmp : 0); pinfo->bklt_ctrl = UNKNOWN_CTRL; data = of_get_property(np, "qcom,mdss-dsi-bl-pmic-control-type", NULL); if (data) { if (!strncmp(data, "bl_ctrl_wled", 12)) { led_trigger_register_simple("bkl-trigger", &bl_led_trigger); pr_debug("%s: SUCCESS-> WLED TRIGGER register\n", __func__); ctrl_pdata->bklt_ctrl = BL_WLED; } else if (!strncmp(data, "bl_ctrl_pwm", 11)) { ctrl_pdata->bklt_ctrl = BL_PWM; #ifdef EXPRESSWIRED spin_lock(&bl_ctrl_lock); gpio_set_value(GPIO_BL_CTRL, 0); udelay(1500); udelay(1500); gpio_set_value(GPIO_BL_CTRL, 1); udelay(200); gpio_set_value(GPIO_BL_CTRL, 0); udelay(300); gpio_set_value(GPIO_BL_CTRL, 1); udelay(400); spin_unlock(&bl_ctrl_lock); #endif #if !defined(CONFIG_BACKLIGHT_IC_KTD2801) rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-pmic-pwm-frequency", &tmp); if (rc) { pr_err("%s:%d, Error, panel pwm_period\n", __func__, __LINE__); return -EINVAL; } ctrl_pdata->pwm_period = tmp; rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-pmic-bank-select", &tmp); if (rc) { pr_err("%s:%d, Error, dsi lpg channel\n", __func__, __LINE__); return -EINVAL; } ctrl_pdata->pwm_lpg_chan = tmp; tmp = of_get_named_gpio(np, "qcom,mdss-dsi-pwm-gpio", 0); ctrl_pdata->pwm_pmic_gpio = tmp; #endif #if defined(CONFIG_BACKLIGHT_IC_KTD2801) #ifndef EXPRESSWIRED msd.bl_ap_pwm= of_get_named_gpio(np, "qcom,bl-wled", 0); if (!gpio_is_valid(msd.bl_ap_pwm)) { pr_err("%s:%d, bl_ap_pwm gpio not specified\n", __func__, __LINE__); } else { rc = gpio_request(msd.bl_ap_pwm, "bl_ap_pwm"); if (rc) { pr_err("request bl_ap_pwm gpio failed, rc=%d\n",rc); gpio_free(msd.bl_ap_pwm); }else{ rc = gpio_tlmm_config(GPIO_CFG(msd.bl_ap_pwm, 0, GPIO_CFG_OUTPUT,GPIO_CFG_NO_PULL,GPIO_CFG_8MA),GPIO_CFG_ENABLE); if (rc) pr_err("request bl_ap_pwm failed, rc=%d\n",rc); } } #endif #endif } else if (!strncmp(data, "bl_ctrl_dcs", 11)) { ctrl_pdata->bklt_ctrl = BL_DCS_CMD; } #if defined(CONFIG_BACKLIGHT_IC_KTD253) else if (!strncmp(data, "bl_ctrl_gpio_swing", 18)) { ctrl_pdata->bklt_ctrl = BL_GPIO_SWING; } #endif } rc = of_property_read_u32(np, "qcom,mdss-brightness-max-level", &tmp); pinfo->brightness_max = (!rc ? tmp : MDSS_MAX_BL_BRIGHTNESS); rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-min-level", &tmp); pinfo->bl_min = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-max-level", &tmp); pinfo->bl_max = (!rc ? tmp : 255); ctrl_pdata->bklt_max = pinfo->bl_max; rc = of_property_read_u32(np, "qcom,mdss-dsi-interleave-mode", &tmp); pinfo->mipi.interleave_mode = (!rc ? tmp : 0); pinfo->mipi.vsync_enable = of_property_read_bool(np, "qcom,mdss-dsi-te-check-enable"); pinfo->mipi.hw_vsync_mode = of_property_read_bool(np, "qcom,mdss-dsi-te-using-te-pin"); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-sync-pulse", &tmp); pinfo->mipi.pulse_mode_hsa_he = (!rc ? tmp : false); pinfo->mipi.hfp_power_stop = of_property_read_bool(np, "qcom,mdss-dsi-hfp-power-mode"); pinfo->mipi.hsa_power_stop = of_property_read_bool(np, "qcom,mdss-dsi-hsa-power-mode"); pinfo->mipi.hbp_power_stop = of_property_read_bool(np, "qcom,mdss-dsi-hbp-power-mode"); pinfo->mipi.bllp_power_stop = of_property_read_bool(np, "qcom,mdss-dsi-bllp-power-mode"); pinfo->mipi.eof_bllp_power_stop = of_property_read_bool( np, "qcom,mdss-dsi-bllp-eof-power-mode"); rc = of_property_read_u32(np, "qcom,mdss-dsi-traffic-mode", &tmp); pinfo->mipi.traffic_mode = (!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE); rc = of_property_read_u32(np, "qcom,mdss-dsi-te-dcs-command", &tmp); pinfo->mipi.insert_dcs_cmd = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-dsi-te-v-sync-continue-lines", &tmp); pinfo->mipi.wr_mem_continue = (!rc ? tmp : 0x3c); rc = of_property_read_u32(np, "qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line", &tmp); pinfo->mipi.wr_mem_start = (!rc ? tmp : 0x2c); rc = of_property_read_u32(np, "qcom,mdss-dsi-te-pin-select", &tmp); pinfo->mipi.te_sel = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-dsi-virtual-channel-id", &tmp); pinfo->mipi.vc = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-color-order", &tmp); pinfo->mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB); rc = of_property_read_u32(np, "qcom,mdss-force-clk-lane-hs", &tmp); pinfo->mipi.force_clk_lane_hs = (!rc ? tmp : 0); pinfo->mipi.data_lane0 = of_property_read_bool(np, "qcom,mdss-dsi-lane-0-state"); pinfo->mipi.data_lane1 = of_property_read_bool(np, "qcom,mdss-dsi-lane-1-state"); pinfo->mipi.data_lane2 = of_property_read_bool(np, "qcom,mdss-dsi-lane-2-state"); pinfo->mipi.data_lane3 = of_property_read_bool(np, "qcom,mdss-dsi-lane-3-state"); rc = of_property_read_u32(np, "qcom,mdss-dsi-lane-map", &tmp); pinfo->mipi.dlane_swap = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-t-clk-pre", &tmp); pinfo->mipi.t_clk_pre = (!rc ? tmp : 0x24); rc = of_property_read_u32(np, "qcom,mdss-dsi-t-clk-post", &tmp); pinfo->mipi.t_clk_post = (!rc ? tmp : 0x03); rc = of_property_read_u32(np, "qcom,mdss-dsi-stream", &tmp); pinfo->mipi.stream = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-mdp-trigger", &tmp); pinfo->mipi.mdp_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (pinfo->mipi.mdp_trigger > 6) { pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger", __func__, __LINE__); pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-dsi-dma-trigger", &tmp); pinfo->mipi.dma_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (pinfo->mipi.dma_trigger > 6) { pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger", __func__, __LINE__); pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW; } data = of_get_property(np, "qcom,mdss-dsi-panel-mode-gpio-state", &tmp); if (data) { if (!strcmp(data, "high")) pinfo->mode_gpio_state = MODE_GPIO_HIGH; else if (!strcmp(data, "low")) pinfo->mode_gpio_state = MODE_GPIO_LOW; } else { pinfo->mode_gpio_state = MODE_GPIO_NOT_VALID; } rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-frame-rate", &tmp); pinfo->mipi.frame_rate = (!rc ? tmp : 60); rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-clock-rate", &tmp); pinfo->clk_rate = (!rc ? tmp : 0); data = of_get_property(np, "qcom,platform-strength-ctrl", &len); if ((!data) || (len != 2)) { pr_err("%s:%d, Unable to read Phy Strength ctrl settings", __func__, __LINE__); return -EINVAL; } pinfo->mipi.dsi_phy_db.strength[0] = data[0]; pinfo->mipi.dsi_phy_db.strength[1] = data[1]; data = of_get_property(np, "qcom,platform-regulator-settings", &len); if ((!data) || (len != 7)) { pr_err("%s:%d, Unable to read Phy regulator settings", __func__, __LINE__); return -EINVAL; } for (i = 0; i < len; i++) { pinfo->mipi.dsi_phy_db.regulator[i] = data[i]; } data = of_get_property(np, "qcom,mdss-dsi-panel-timings", &len); if ((!data) || (len != 12)) { pr_err("%s:%d, Unable to read Phy timing settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) pinfo->mipi.dsi_phy_db.timing[i] = data[i]; pinfo->mipi.lp11_init = of_property_read_bool(np, "qcom,mdss-dsi-lp11-init"); rc = of_property_read_u32(np, "qcom,mdss-dsi-init-delay-us", &tmp); pinfo->mipi.init_delay = (!rc ? tmp : 0); mdss_dsi_parse_fbc_params(np, pinfo); if(lcd_id == 0x55bc90){ //BOE mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds, "qcom,mdss-dsi-on-command", "qcom,mdss-dsi-on-command-state"); }else if(lcd_id == 0x558cc0){ //SDC mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds, "qcom,mdss-dsi-on-sdc-command", "qcom,mdss-dsi-on-command-state"); }else{ mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->on_cmds, "qcom,mdss-dsi-on-command", "qcom,mdss-dsi-on-command-state"); } mdss_dsi_parse_dcs_cmds(np, &ctrl_pdata->off_cmds, "qcom,mdss-dsi-off-command", "qcom,mdss-dsi-off-command-state"); return 0; error: return -EINVAL; }
static int mdss_panel_parse_dt(struct device_node *np, struct mdss_panel_common_pdata *panel_data) { u32 tmp; int rc, i, len; const char *data; static const char *pdest; rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-width", &tmp); if (rc) { pr_err("%s:%d, panel width not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.xres = (!rc ? tmp : 640); rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-height", &tmp); if (rc) { pr_err("%s:%d, panel height not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.yres = (!rc ? tmp : 480); rc = of_property_read_u32(np, "qcom,mdss-pan-physical-width-dimension", &tmp); panel_data->panel_info.physical_width = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-physical-height-dimension", &tmp); panel_data->panel_info.physical_height = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-left-border", &tmp); panel_data->panel_info.lcdc.xres_pad = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-right-border", &tmp); if (!rc) panel_data->panel_info.lcdc.xres_pad += tmp; rc = of_property_read_u32(np, "qcom,mdss-dsi-v-top-border", &tmp); panel_data->panel_info.lcdc.yres_pad = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-v-bottom-border", &tmp); if (!rc) panel_data->panel_info.lcdc.yres_pad += tmp; rc = of_property_read_u32(np, "qcom,mdss-dsi-bpp", &tmp); if (rc) { pr_err("%s:%d, bpp not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.bpp = (!rc ? tmp : 24); panel_data->panel_info.mipi.mode = DSI_VIDEO_MODE; data = of_get_property(np, "qcom,mdss-dsi-panel-type", NULL); if (data && !strncmp(data, "dsi_cmd_mode", 12)) panel_data->panel_info.mipi.mode = DSI_CMD_MODE; rc = of_property_read_u32(np, "qcom,mdss-dsi-pixel-packing", &tmp); tmp = (!rc ? tmp : 0); rc = mdss_panel_dt_get_dst_fmt(panel_data->panel_info.bpp, panel_data->panel_info.mipi.mode, tmp, &(panel_data->panel_info.mipi.dst_format)); if (rc) { pr_debug("%s: problem determining dst format. Set Default\n", __func__); panel_data->panel_info.mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888; } pdest = of_get_property(np, "qcom,mdss-dsi-panel-destination", NULL); if (strlen(pdest) != 9) { pr_err("%s: Unknown pdest specified\n", __func__); return -EINVAL; } if (!strncmp(pdest, "display_1", 9)) panel_data->panel_info.pdest = DISPLAY_1; else if (!strncmp(pdest, "display_2", 9)) panel_data->panel_info.pdest = DISPLAY_2; else { pr_debug("%s: pdest not specified. Set Default\n", __func__); panel_data->panel_info.pdest = DISPLAY_1; } rc = of_property_read_u32(np, "qcom,mdss-dsi-h-front-porch", &tmp); panel_data->panel_info.lcdc.h_front_porch = (!rc ? tmp : 6); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-back-porch", &tmp); panel_data->panel_info.lcdc.h_back_porch = (!rc ? tmp : 6); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-pulse-width", &tmp); panel_data->panel_info.lcdc.h_pulse_width = (!rc ? tmp : 2); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-sync-skew", &tmp); panel_data->panel_info.lcdc.hsync_skew = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-v-back-porch", &tmp); panel_data->panel_info.lcdc.v_back_porch = (!rc ? tmp : 6); rc = of_property_read_u32(np, "qcom,mdss-dsi-v-front-porch", &tmp); panel_data->panel_info.lcdc.v_front_porch = (!rc ? tmp : 6); rc = of_property_read_u32(np, "qcom,mdss-dsi-v-pulse-width", &tmp); panel_data->panel_info.lcdc.v_pulse_width = (!rc ? tmp : 2); rc = of_property_read_u32(np, "qcom,mdss-dsi-underflow-color", &tmp); panel_data->panel_info.lcdc.underflow_clr = (!rc ? tmp : 0xff); rc = of_property_read_u32(np, "qcom,mdss-dsi-border-color", &tmp); panel_data->panel_info.lcdc.border_clr = (!rc ? tmp : 0); panel_data->panel_info.bklt_ctrl = UNKNOWN_CTRL; data = of_get_property(np, "qcom,mdss-dsi-bl-pmic-control-type", NULL); if (data) { if (!strncmp(data, "bl_ctrl_wled", 12)) { led_trigger_register_simple("bkl-trigger", &bl_led_trigger); pr_debug("%s: SUCCESS-> WLED TRIGGER register\n", __func__); panel_data->panel_info.bklt_ctrl = BL_WLED; } else if (!strncmp(data, "bl_ctrl_pwm", 11)) { panel_data->panel_info.bklt_ctrl = BL_PWM; rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-pmic-pwm-frequency", &tmp); if (rc) { pr_err("%s:%d, Error, panel pwm_period\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.pwm_period = tmp; rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-pmic-bank-select", &tmp); if (rc) { pr_err("%s:%d, Error, dsi lpg channel\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.pwm_lpg_chan = tmp; tmp = of_get_named_gpio(np, "qcom,mdss-dsi-pwm-gpio", 0); panel_data->panel_info.pwm_pmic_gpio = tmp; } else if (!strncmp(data, "bl_ctrl_dcs", 11)) { panel_data->panel_info.bklt_ctrl = BL_DCS_CMD; } } rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-min-level", &tmp); panel_data->panel_info.bl_min = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-bl-max-level", &tmp); panel_data->panel_info.bl_max = (!rc ? tmp : 255); rc = of_property_read_u32(np, "qcom,mdss-dsi-interleave-mode", &tmp); panel_data->panel_info.mipi.interleave_mode = (!rc ? tmp : 0); panel_data->panel_info.mipi.vsync_enable = of_property_read_bool(np, "qcom,mdss-dsi-te-check-enable"); panel_data->panel_info.mipi.hw_vsync_mode = of_property_read_bool(np, "qcom,mdss-dsi-te-using-te-pin"); rc = of_property_read_u32(np, "qcom,mdss-dsi-h-sync-pulse", &tmp); panel_data->panel_info.mipi.pulse_mode_hsa_he = (!rc ? tmp : false); panel_data->panel_info.mipi.hfp_power_stop = of_property_read_bool(np, "qcom,mdss-dsi-hfp-power-mode"); panel_data->panel_info.mipi.hsa_power_stop = of_property_read_bool(np, "qcom,mdss-dsi-hsa-power-mode"); panel_data->panel_info.mipi.hbp_power_stop = of_property_read_bool(np, "qcom,mdss-dsi-hbp-power-mode"); panel_data->panel_info.mipi.bllp_power_stop = of_property_read_bool(np, "qcom,mdss-dsi-bllp-power-mode"); panel_data->panel_info.mipi.eof_bllp_power_stop = of_property_read_bool( np, "qcom,mdss-dsi-bllp-eof-power-mode"); rc = of_property_read_u32(np, "qcom,mdss-dsi-traffic-mode", &tmp); panel_data->panel_info.mipi.traffic_mode = (!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE); rc = of_property_read_u32(np, "qcom,mdss-dsi-te-dcs-command", &tmp); panel_data->panel_info.mipi.insert_dcs_cmd = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-dsi-te-v-sync-continue-lines", &tmp); panel_data->panel_info.mipi.wr_mem_continue = (!rc ? tmp : 0x3c); rc = of_property_read_u32(np, "qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line", &tmp); panel_data->panel_info.mipi.wr_mem_start = (!rc ? tmp : 0x2c); rc = of_property_read_u32(np, "qcom,mdss-dsi-te-pin-select", &tmp); panel_data->panel_info.mipi.te_sel = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-dsi-virtual-channel-id", &tmp); panel_data->panel_info.mipi.vc = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-color-order", &tmp); panel_data->panel_info.mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB); panel_data->panel_info.mipi.data_lane0 = of_property_read_bool(np, "qcom,mdss-dsi-lane-0-state"); panel_data->panel_info.mipi.data_lane1 = of_property_read_bool(np, "qcom,mdss-dsi-lane-1-state"); panel_data->panel_info.mipi.data_lane2 = of_property_read_bool(np, "qcom,mdss-dsi-lane-2-state"); panel_data->panel_info.mipi.data_lane3 = of_property_read_bool(np, "qcom,mdss-dsi-lane-3-state"); rc = of_property_read_u32(np, "qcom,mdss-dsi-lane-map", &tmp); panel_data->panel_info.mipi.dlane_swap = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-t-clk-pre", &tmp); panel_data->panel_info.mipi.t_clk_pre = (!rc ? tmp : 0x24); rc = of_property_read_u32(np, "qcom,mdss-dsi-t-clk-post", &tmp); panel_data->panel_info.mipi.t_clk_post = (!rc ? tmp : 0x03); rc = of_property_read_u32(np, "qcom,mdss-dsi-stream", &tmp); panel_data->panel_info.mipi.stream = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-dsi-mdp-trigger", &tmp); panel_data->panel_info.mipi.mdp_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (panel_data->panel_info.mipi.mdp_trigger > 6) { pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger", __func__, __LINE__); panel_data->panel_info.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-dsi-dma-trigger", &tmp); panel_data->panel_info.mipi.dma_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (panel_data->panel_info.mipi.dma_trigger > 6) { pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger", __func__, __LINE__); panel_data->panel_info.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-frame-rate", &tmp); panel_data->panel_info.mipi.frame_rate = (!rc ? tmp : 60); rc = of_property_read_u32(np, "qcom,mdss-dsi-panel-clock-rate", &tmp); panel_data->panel_info.clk_rate = (!rc ? tmp : 0); data = of_get_property(np, "qcom,mdss-dsi-panel-timings", &len); if ((!data) || (len != 12)) { pr_err("%s:%d, Unable to read Phy timing settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.timing[i] = data[i]; panel_data->panel_info.mipi.dsi_phy_db = &phy_params; mdss_dsi_parse_fbc_params(np, &panel_data->panel_info); mdss_dsi_parse_dcs_cmds(np, &panel_data->on_cmds, "qcom,mdss-dsi-on-command", "qcom,mdss-dsi-on-command-state"); mdss_dsi_parse_dcs_cmds(np, &panel_data->off_cmds, "qcom,mdss-dsi-off-command", "qcom,mdss-dsi-off-command-state"); return 0; error: return -EINVAL; }