C++ (Cpp) mdss_dsi_uniphy_pll_lock_detect_setting Examples

Example #1

File: target_display.c Project: detule/lk-g2-spr

static uint32_t dsi_pll_enable_seq(uint32_t ctl_base)
{
	uint32_t rc = 0;

	mdss_dsi_uniphy_pll_sw_reset(ctl_base);

	writel(0x01, ctl_base + 0x0220); /* GLB CFG */
	mdelay(1);
	writel(0x05, ctl_base + 0x0220); /* GLB CFG */
	mdelay(1);
	writel(0x07, ctl_base + 0x0220); /* GLB CFG */
	mdelay(1);
	writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
	mdelay(1);

	mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);

	while (!(readl(ctl_base + 0x02c0) & 0x01)) {
		mdss_dsi_uniphy_pll_sw_reset(ctl_base);
		writel(0x01, ctl_base + 0x0220); /* GLB CFG */
		mdelay(1);
		writel(0x05, ctl_base + 0x0220); /* GLB CFG */
		mdelay(1);
		writel(0x07, ctl_base + 0x0220); /* GLB CFG */
		mdelay(1);
		writel(0x05, ctl_base + 0x0220); /* GLB CFG */
		mdelay(1);
		writel(0x07, ctl_base + 0x0220); /* GLB CFG */
		mdelay(1);
		writel(0x0f, ctl_base + 0x0220); /* GLB CFG */
		mdelay(2);
		mdss_dsi_uniphy_pll_lock_detect_setting(ctl_base);
	}
	return rc;
}

Example #2

File: target_display.c Project: sndnvaps/lk-1

static uint32_t dsi_pll_enable_seq_m(uint32_t pll_base)
{
	uint32_t i = 0;
	uint32_t pll_locked = 0;

	mdss_dsi_uniphy_pll_sw_reset(pll_base);

	/*
	 * Add hardware recommended delays between register writes for
	 * the updates to take effect. These delays are necessary for the
	 * PLL to successfully lock
	 */
	writel(0x01, pll_base + 0x0020); /* GLB CFG */
	udelay(200);
	writel(0x05, pll_base + 0x0020); /* GLB CFG */
	udelay(200);
	writel(0x0f, pll_base + 0x0020); /* GLB CFG */
	udelay(1000);

	mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
	pll_locked = readl(pll_base + 0x00c0) & 0x01;
	for (i = 0; (i < 4) && !pll_locked; i++) {
		writel(0x07, pll_base + 0x0020); /* GLB CFG */
		if (i != 0)
			writel(0x34, pll_base + 0x00070); /* CAL CFG1*/
		udelay(1);
		writel(0x0f, pll_base + 0x0020); /* GLB CFG */
		udelay(1000);
		mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
		pll_locked = readl(pll_base + 0x00c0) & 0x01;
	}

	return pll_locked;
}

Example #3

File: target_display.c Project: sndnvaps/lk-1

static uint32_t dsi_pll_enable_seq_f1(uint32_t pll_base)
{
	uint32_t pll_locked = 0;

	mdss_dsi_uniphy_pll_sw_reset(pll_base);

	/*
	 * Add hardware recommended delays between register writes for
	 * the updates to take effect. These delays are necessary for the
	 * PLL to successfully lock
	 */
	writel(0x01, pll_base + 0x0020); /* GLB CFG */
	udelay(200);
	writel(0x05, pll_base + 0x0020); /* GLB CFG */
	udelay(200);
	writel(0x0f, pll_base + 0x0020); /* GLB CFG */
	udelay(200);
	writel(0x0d, pll_base + 0x0020); /* GLB CFG */
	udelay(200);
	writel(0x0f, pll_base + 0x0020); /* GLB CFG */
	udelay(1000);

	mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);
	pll_locked = readl(pll_base + 0x00c0) & 0x01;

	return pll_locked;
}

Example #4

File: target_display.c Project: M1cha/lktris

static uint32_t dsi_pll_lock_status(uint32_t pll_base)
{
	uint32_t counter, status;

	udelay(100);
	mdss_dsi_uniphy_pll_lock_detect_setting(pll_base);

	status = readl(pll_base + 0x00c0) & 0x01;
	for (counter = 0; counter < 5 && !status; counter++) {
		udelay(100);
		status = readl(pll_base + 0x00c0) & 0x01;
	}

	return status;
}

Example #5

File: clock-mdss-8974.c Project: miing/lmkp_msm

static int __mdss_dsi_pll_enable(struct clk *c)
{
	u32 status;
	u32 max_reads, timeout_us;
	int i;

	if (!pll_initialized) {
		if (dsi_pll_rate)
			__mdss_dsi_pll_byte_set_rate(c, dsi_pll_rate);
		else
			pr_err("%s: Calling clk_en before set_rate\n",
						__func__);
	}

	mdss_dsi_uniphy_pll_sw_reset();
	/* PLL power up */
	/* Add HW recommended delay between
	   register writes for the update to propagate */
	REG_W(0x01, mdss_dsi_base + 0x0220); /* GLB CFG */
	udelay(1000);
	REG_W(0x05, mdss_dsi_base + 0x0220); /* GLB CFG */
	udelay(1000);
	REG_W(0x07, mdss_dsi_base + 0x0220); /* GLB CFG */
	udelay(1000);
	REG_W(0x0f, mdss_dsi_base + 0x0220); /* GLB CFG */
	udelay(1000);

	for (i = 0; i < 3; i++) {
		mdss_dsi_uniphy_pll_lock_detect_setting();
		/* poll for PLL ready status */
		max_reads = 5;
		timeout_us = 100;
		if (readl_poll_timeout_noirq((mdss_dsi_base + 0x02c0),
				   status,
				   ((status & 0x01) == 1),
					     max_reads, timeout_us)) {
			pr_debug("%s: DSI PLL status=%x failed to Lock\n",
			       __func__, status);
			pr_debug("%s:Trying to power UP PLL again\n",
			       __func__);
		} else
			break;

		mdss_dsi_uniphy_pll_sw_reset();
		udelay(1000);
		/* Add HW recommended delay between
		   register writes for the update to propagate */
		REG_W(0x01, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x05, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x07, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x05, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x07, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(1000);
		REG_W(0x0f, mdss_dsi_base + 0x0220); /* GLB CFG */
		udelay(2000);

	}

	if ((status & 0x01) != 1) {
		pr_err("%s: DSI PLL status=%x failed to Lock\n",
		       __func__, status);
		return -EINVAL;
	}

	pr_debug("%s: **** PLL Lock success\n", __func__);

	return 0;
}