int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { int ret = NO_ERROR; uint32_t intf_sel = 0x100; uint32_t left_pipe, right_pipe; uint32_t reg; mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE); if (pinfo->mipi.dual_dsi) { mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE); } mdp_clk_gating_ctrl(); mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); mdss_vbif_setup(); mdss_smp_setup(pinfo, left_pipe, right_pipe); mdss_qos_remapper_setup(); mdss_vbif_qos_remapper_setup(pinfo); mdss_source_pipe_config(fb, pinfo, left_pipe); if (pinfo->lcdc.dual_pipe) mdss_source_pipe_config(fb, pinfo, right_pipe); mdss_layer_mixer_setup(fb, pinfo); reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); writel(reg, MDP_CTL_0_BASE + CTL_TOP); /*If dst_split is enabled only intf 2 needs to be enabled. CTL_1 path should not be set since CTL_0 itself is going to split after DSPP block*/ if (pinfo->fbc.enabled) mdss_fbc_cfg(pinfo); if (pinfo->mipi.dual_dsi) { if (!pinfo->lcdc.dst_split) { reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); writel(reg, MDP_CTL_1_BASE + CTL_TOP); } intf_sel |= BIT(16); /* INTF 2 enable */ } writel(intf_sel, MDP_DISP_INTF_SEL); writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); return ret; }
int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { int ret = NO_ERROR; struct lcdc_panel_info *lcdc = NULL; mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); mdp_clk_gating_ctrl(); mdss_vbif_setup(); mdss_smp_setup(pinfo); writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0); mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE); if (pinfo->lcdc.dual_pipe) mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE); mdss_layer_mixer_setup(fb, pinfo); if (pinfo->lcdc.dual_pipe) writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); else writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); writel(0x9, MDP_DISP_INTF_SEL); writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); return 0; }
int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { int ret = NO_ERROR; uint32_t left_pipe, right_pipe; mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE); mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); mdp_clk_gating_ctrl(); mdss_vbif_setup(); mdss_smp_setup(pinfo, left_pipe, right_pipe); mdss_qos_remapper_setup(); mdss_source_pipe_config(fb, pinfo, left_pipe); if (pinfo->lcdc.dual_pipe) mdss_source_pipe_config(fb, pinfo, right_pipe); mdss_layer_mixer_setup(fb, pinfo); if (pinfo->lcdc.dual_pipe) writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); else writel(0x40, MDP_CTL_0_BASE + CTL_TOP); writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); return ret; }
int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { uint32_t left_pipe, right_pipe; dprintf(SPEW, "ENTER: %s\n", __func__); mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE + mdss_mdp_intf_offset()); pinfo->pipe_type = MDSS_MDP_PIPE_TYPE_RGB; mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); mdp_clk_gating_ctrl(); mdss_vbif_setup(); mdss_smp_setup(pinfo, left_pipe, right_pipe); mdss_qos_remapper_setup(); mdss_source_pipe_config(fb, pinfo, left_pipe); if (pinfo->lcdc.dual_pipe) mdss_source_pipe_config(fb, pinfo, right_pipe); mdss_layer_mixer_setup(fb, pinfo); if (pinfo->lcdc.dual_pipe) writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); else writel(0x40, MDP_CTL_0_BASE + CTL_TOP); writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); return 0; }
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { int ret = NO_ERROR; struct lcdc_panel_info *lcdc = NULL; uint32_t intf_sel = 0x100; mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); if (pinfo->mipi.dual_dsi) mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); mdp_clk_gating_ctrl(); mdss_vbif_setup(); mdss_smp_setup(pinfo); writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0); mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE); if (pinfo->lcdc.dual_pipe) mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_1_BASE); mdss_layer_mixer_setup(fb, pinfo); writel(0x1F20, MDP_CTL_0_BASE + CTL_TOP); if (pinfo->mipi.dual_dsi) { writel(0x1F30, MDP_CTL_1_BASE + CTL_TOP); intf_sel |= BIT(16); /* INTF 2 enable */ } writel(intf_sel, MDP_DISP_INTF_SEL); writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); return 0; }
int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { int ret = NO_ERROR; struct lcdc_panel_info *lcdc = NULL; uint32_t left_pipe, right_pipe; mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); switch (pinfo->pipe_type) { case MDSS_MDP_PIPE_TYPE_RGB: left_pipe = MDP_VP_0_RGB_0_BASE; right_pipe = MDP_VP_0_RGB_1_BASE; break; case MDSS_MDP_PIPE_TYPE_DMA: left_pipe = MDP_VP_0_DMA_0_BASE; right_pipe = MDP_VP_0_DMA_1_BASE; break; case MDSS_MDP_PIPE_TYPE_VIG: default: left_pipe = MDP_VP_0_VIG_0_BASE; right_pipe = MDP_VP_0_VIG_1_BASE; break; } mdp_clk_gating_ctrl(); mdss_vbif_setup(); mdss_smp_setup(pinfo, left_pipe, right_pipe); mdss_qos_remapper_setup(); mdss_source_pipe_config(fb, pinfo, left_pipe); if (pinfo->lcdc.dual_pipe) mdss_source_pipe_config(fb, pinfo, right_pipe); mdss_layer_mixer_setup(fb, pinfo); if (pinfo->lcdc.dual_pipe) writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); else writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); writel(0x9, MDP_DISP_INTF_SEL); writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); return 0; }
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { int ret = NO_ERROR; struct lcdc_panel_info *lcdc = NULL; uint32_t intf_sel = 0x100; uint32_t left_pipe, right_pipe; mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE); if (pinfo->mipi.dual_dsi) { mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE); } mdp_clk_gating_ctrl(); switch (pinfo->pipe_type) { case MDSS_MDP_PIPE_TYPE_RGB: left_pipe = MDP_VP_0_RGB_0_BASE; right_pipe = MDP_VP_0_RGB_1_BASE; break; case MDSS_MDP_PIPE_TYPE_DMA: left_pipe = MDP_VP_0_DMA_0_BASE; right_pipe = MDP_VP_0_DMA_1_BASE; break; case MDSS_MDP_PIPE_TYPE_VIG: default: left_pipe = MDP_VP_0_VIG_0_BASE; right_pipe = MDP_VP_0_VIG_1_BASE; break; } mdss_vbif_setup(); mdss_smp_setup(pinfo, left_pipe, right_pipe); mdss_qos_remapper_setup(); mdss_source_pipe_config(fb, pinfo, left_pipe); if (pinfo->lcdc.dual_pipe) mdss_source_pipe_config(fb, pinfo, right_pipe); mdss_layer_mixer_setup(fb, pinfo); writel(0x1F20, MDP_CTL_0_BASE + CTL_TOP); /*If dst_split is enabled only intf 2 needs to be enabled. CTL_1 path should not be set since CTL_0 itself is going to split after DSPP block*/ if (pinfo->mipi.dual_dsi) { if (!pinfo->lcdc.dst_split) writel(0x1F30, MDP_CTL_1_BASE + CTL_TOP); intf_sel |= BIT(16); /* INTF 2 enable */ } writel(intf_sel, MDP_DISP_INTF_SEL); writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); return 0; }
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) { uint32_t intf_sel, sintf_sel; uint32_t intf_base, sintf_base; uint32_t left_pipe, right_pipe; uint32_t reg; mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base); mdss_intf_tg_setup(pinfo, intf_base); mdss_intf_fetch_start_config(pinfo, intf_base); if (pinfo->mipi.dual_dsi) { mdss_intf_tg_setup(pinfo, sintf_base); mdss_intf_fetch_start_config(pinfo, sintf_base); } mdp_clk_gating_ctrl(); mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); mdss_vbif_setup(); if (!has_fixed_size_smp()) mdss_smp_setup(pinfo, left_pipe, right_pipe); mdss_qos_remapper_setup(); mdss_vbif_qos_remapper_setup(pinfo); mdss_source_pipe_config(fb, pinfo, left_pipe); if (pinfo->lcdc.dual_pipe) mdss_source_pipe_config(fb, pinfo, right_pipe); mdss_layer_mixer_setup(fb, pinfo); reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); /* enable 3D mux for dual_pipe but single interface config */ if (pinfo->lcdc.dual_pipe && !pinfo->mipi.dual_dsi && !pinfo->lcdc.split_display) reg |= BIT(19) | BIT(20); writel(reg, MDP_CTL_0_BASE + CTL_TOP); /*If dst_split is enabled only intf 2 needs to be enabled. CTL_1 path should not be set since CTL_0 itself is going to split after DSPP block*/ if (pinfo->fbc.enabled) mdss_fbc_cfg(pinfo); if (pinfo->mipi.dual_dsi) { if (!pinfo->lcdc.dst_split) { reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); writel(reg, MDP_CTL_1_BASE + CTL_TOP); } intf_sel |= sintf_sel; /* INTF 2 enable */ } writel(intf_sel, MDP_DISP_INTF_SEL); writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); return 0; }