DRIVER_INIT_MEMBER(okean240_state,okean240)
{
UINT8 *RAM = memregion("maincpu")->base();
membank("boot")->configure_entries(0, 2, &RAM[0x0000], 0xe000);
}
void mc1000_state::machine_start()
{
address_space &program = m_maincpu->space(AS_PROGRAM);
/* setup memory banking */
UINT8 *rom = m_rom->base();
program.install_readwrite_bank(0x0000, 0x1fff, "bank1");
membank("bank1")->configure_entry(0, rom);
membank("bank1")->configure_entry(1, rom + 0xc000);
membank("bank1")->set_entry(1);
m_rom0000 = 1;
program.install_readwrite_bank(0x2000, 0x27ff, "bank2");
membank("bank2")->configure_entry(0, rom + 0x2000);
membank("bank2")->configure_entry(1, m_mc6845_video_ram);
membank("bank2")->set_entry(0);
membank("bank3")->configure_entry(0, rom + 0x4000);
membank("bank3")->set_entry(0);
membank("bank4")->configure_entry(0, m_mc6847_video_ram);
membank("bank4")->configure_entry(1, rom + 0x8000);
membank("bank4")->set_entry(0);
membank("bank5")->configure_entry(0, rom + 0x9800);
membank("bank5")->set_entry(0);
bankswitch();
/* register for state saving */
save_item(NAME(m_rom0000));
save_item(NAME(m_mc6845_bank));
save_item(NAME(m_mc6847_bank));
save_item(NAME(m_keylatch));
save_item(NAME(m_hsync));
save_item(NAME(m_vsync));
}
void nes_state::machine_start()
{
for (int i = 0; i < 9; i++)
{
char str[7];
sprintf(str, "FCKEY%i", i);
m_io_fckey[i] = ioport(str);
}
for (int i = 0; i < 13; i++)
{
char str[9];
sprintf(str, "SUBKEY%i", i);
m_io_subkey[i] = ioport(str);
}
for (int i = 0; i < 4; i++)
{
char str[8];
sprintf(str, "PAD%i", i + 1);
m_io_pad[i] = ioport(str);
sprintf(str, "MAH%i", i);
m_io_mahjong[i] = ioport(str);
sprintf(str, "FT_COL%i", i);
m_io_ftrainer[i] = ioport(str);
}
m_io_ctrlsel = ioport("CTRLSEL");
m_io_exp = ioport("EXP");
m_io_paddle = ioport("PADDLE");
m_io_paddle_btn = ioport("PADDLE_BUTTON");
m_io_cc_left = ioport("CC_LEFT");
m_io_cc_right = ioport("CC_RIGHT");
m_io_zapper1_t = ioport("ZAPPER1_T");
m_io_zapper1_x = ioport("ZAPPER1_X");
m_io_zapper1_y = ioport("ZAPPER1_Y");
m_io_zapper2_t = ioport("ZAPPER2_T");
m_io_zapper2_x = ioport("ZAPPER2_X");
m_io_zapper2_y = ioport("ZAPPER2_Y");
m_io_powerpad[0] = ioport("POWERPAD1");
m_io_powerpad[1] = ioport("POWERPAD2");
address_space &space = m_maincpu->space(AS_PROGRAM);
// CIRAM (Character Internal RAM)
// NES has 2KB of internal RAM which can be used to fill the 4x1KB banks of PPU RAM at $2000-$2fff
// Line A10 is exposed to the carts, so that games can change CIRAM mapping in PPU (we emulate this with the set_nt_mirroring
// function). CIRAM can also be disabled by the game (if e.g. VROM or cart RAM has to be used in PPU...
m_ciram = auto_alloc_array(machine(), UINT8, 0x800);
// other pointers got set in the loading routine, because they 'belong' to the cart itself
if (m_cartslot && m_cartslot->m_cart)
{
// Set up memory handlers
space.install_read_handler(0x4100, 0x5fff, read8_delegate(FUNC(nes_cart_slot_device::read_l), (nes_cart_slot_device *)m_cartslot));
space.install_write_handler(0x4100, 0x5fff, write8_delegate(FUNC(nes_cart_slot_device::write_l), (nes_cart_slot_device *)m_cartslot));
space.install_read_handler(0x6000, 0x7fff, read8_delegate(FUNC(nes_cart_slot_device::read_m), (nes_cart_slot_device *)m_cartslot));
space.install_write_handler(0x6000, 0x7fff, write8_delegate(FUNC(nes_cart_slot_device::write_m), (nes_cart_slot_device *)m_cartslot));
space.install_read_bank(0x8000, 0x9fff, "prg0");
space.install_read_bank(0xa000, 0xbfff, "prg1");
space.install_read_bank(0xc000, 0xdfff, "prg2");
space.install_read_bank(0xe000, 0xffff, "prg3");
space.install_write_handler(0x8000, 0xffff, write8_delegate(FUNC(nes_cart_slot_device::write_h), (nes_cart_slot_device *)m_cartslot));
m_cartslot->pcb_start(m_ciram);
m_cartslot->m_cart->pcb_reg_postload(machine());
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0, 0x1fff, read8_delegate(FUNC(device_nes_cart_interface::chr_r),m_cartslot->m_cart), write8_delegate(FUNC(device_nes_cart_interface::chr_w),m_cartslot->m_cart));
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(device_nes_cart_interface::nt_r),m_cartslot->m_cart), write8_delegate(FUNC(device_nes_cart_interface::nt_w),m_cartslot->m_cart));
m_ppu->set_scanline_callback(ppu2c0x_scanline_delegate(FUNC(device_nes_cart_interface::scanline_irq),m_cartslot->m_cart));
m_ppu->set_hblank_callback(ppu2c0x_hblank_delegate(FUNC(device_nes_cart_interface::hblank_irq),m_cartslot->m_cart));
m_ppu->set_latch(ppu2c0x_latch_delegate(FUNC(device_nes_cart_interface::ppu_latch),m_cartslot->m_cart));
// install additional handlers (read_h, read_ex, write_ex)
if (m_cartslot->get_pcb_id() == STD_EXROM || m_cartslot->get_pcb_id() == STD_NROM368
|| m_cartslot->get_pcb_id() == GG_NROM || m_cartslot->get_pcb_id() == CAMERICA_ALADDIN || m_cartslot->get_pcb_id() == SUNSOFT_DCS
|| m_cartslot->get_pcb_id() == BANDAI_DATACH || m_cartslot->get_pcb_id() == BANDAI_KARAOKE || m_cartslot->get_pcb_id() == BTL_2A03_PURITANS || m_cartslot->get_pcb_id() == AVE_MAXI15
|| m_cartslot->get_pcb_id() == KAISER_KS7022 || m_cartslot->get_pcb_id() == KAISER_KS7031 || m_cartslot->get_pcb_id() == BMC_VT5201
|| m_cartslot->get_pcb_id() == UNL_LH32 || m_cartslot->get_pcb_id() == UNL_LH10 || m_cartslot->get_pcb_id() == UNL_2708
|| m_cartslot->get_pcb_id() == UNL_43272 || m_cartslot->get_pcb_id() == BMC_G63IN1 || m_cartslot->get_pcb_id() == BMC_8157
|| m_cartslot->get_pcb_id() == BMC_GOLD150 || m_cartslot->get_pcb_id() == BMC_CH001
|| m_cartslot->get_pcb_id() == BMC_70IN1 || m_cartslot->get_pcb_id() == BMC_800IN1)
{
logerror("read_h installed!\n");
space.install_read_handler(0x8000, 0xffff, read8_delegate(FUNC(nes_cart_slot_device::read_h), (nes_cart_slot_device *)m_cartslot));
}
if (m_cartslot->get_pcb_id() == BTL_SMB2JB || m_cartslot->get_pcb_id() == UNL_AC08 || m_cartslot->get_pcb_id() == UNL_SMB2J || m_cartslot->get_pcb_id() == BTL_09034A)
{
logerror("write_ex installed!\n");
space.install_write_handler(0x4020, 0x40ff, write8_delegate(FUNC(nes_cart_slot_device::write_ex), (nes_cart_slot_device *)m_cartslot));
}
if (m_cartslot->get_pcb_id() == KAISER_KS7017 || m_cartslot->get_pcb_id() == UNL_603_5052)
{
logerror("write_ex & read_ex installed!\n");
space.install_read_handler(0x4020, 0x40ff, read8_delegate(FUNC(nes_cart_slot_device::read_ex), (nes_cart_slot_device *)m_cartslot));
space.install_write_handler(0x4020, 0x40ff, write8_delegate(FUNC(nes_cart_slot_device::write_ex), (nes_cart_slot_device *)m_cartslot));
}
}
else if (m_disk_expansion) // if there is Disk Expansion and no cart has been loaded, setup memory accordingly
{
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0, 0x1fff, read8_delegate(FUNC(nes_state::fds_chr_r),this), write8_delegate(FUNC(nes_state::fds_chr_w),this));
m_ppu->space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(nes_state::fds_nt_r),this), write8_delegate(FUNC(nes_state::fds_nt_w),this));
if (!m_fds_ram)
m_fds_ram = auto_alloc_array(machine(), UINT8, 0x8000);
if (!m_vram)
m_vram = auto_alloc_array(machine(), UINT8, 0x2000);
space.install_read_handler(0x4030, 0x403f, read8_delegate(FUNC(nes_state::nes_fds_r),this));
space.install_read_bank(0x6000, 0xdfff, "fdsram");
space.install_read_bank(0xe000, 0xffff, "bank1");
space.install_write_handler(0x4020, 0x402f, write8_delegate(FUNC(nes_state::nes_fds_w),this));
space.install_write_bank(0x6000, 0xdfff, "fdsram");
membank("bank1")->set_base(machine().root_device().memregion("maincpu")->base() + 0xe000);
membank("fdsram")->set_base(m_fds_ram);
}
state_register();
}
DRIVER_INIT_MEMBER(argo_state,argo)
{
UINT8 *RAM = memregion("maincpu")->base();
membank("boot")->configure_entries(0, 2, &RAM[0x0000], 0xf800);
}
void partner_state::partner_bank_switch()
{
address_space &space = m_maincpu->space(AS_PROGRAM);
UINT8 *rom = memregion("maincpu")->base();
UINT8 *ram = m_ram->pointer();
space.install_write_bank(0x0000, 0x07ff, "bank1");
space.install_write_bank(0x0800, 0x3fff, "bank2");
space.install_write_bank(0x4000, 0x5fff, "bank3");
space.install_write_bank(0x6000, 0x7fff, "bank4");
space.install_write_bank(0x8000, 0x9fff, "bank5");
space.install_write_bank(0xa000, 0xb7ff, "bank6");
space.install_write_bank(0xb800, 0xbfff, "bank7");
space.install_write_bank(0xc000, 0xc7ff, "bank8");
space.install_write_bank(0xc800, 0xcfff, "bank9");
space.install_write_bank(0xd000, 0xd7ff, "bank10");
space.unmap_write(0xdc00, 0xddff);
space.install_read_bank (0xdc00, 0xddff, "bank11");
space.unmap_write(0xe000, 0xe7ff);
space.unmap_write(0xe800, 0xffff);
// BANK 1 (0x0000 - 0x07ff)
if (m_mem_page==0) {
space.unmap_write(0x0000, 0x07ff);
membank("bank1")->set_base(rom + 0x10000);
} else {
if (m_mem_page==7) {
membank("bank1")->set_base(ram + 0x8000);
} else {
membank("bank1")->set_base(ram + 0x0000);
}
}
// BANK 2 (0x0800 - 0x3fff)
if (m_mem_page==7) {
membank("bank2")->set_base(ram + 0x8800);
} else {
membank("bank2")->set_base(ram + 0x0800);
}
// BANK 3 (0x4000 - 0x5fff)
if (m_mem_page==7) {
membank("bank3")->set_base(ram + 0xC000);
} else {
if (m_mem_page==10) {
//window 1
space.unmap_write(0x4000, 0x5fff);
partner_window_1(3, 0, rom);
} else {
membank("bank3")->set_base(ram + 0x4000);
}
}
// BANK 4 (0x6000 - 0x7fff)
if (m_mem_page==7) {
membank("bank4")->set_base(ram + 0xe000);
} else {
membank("bank4")->set_base(ram + 0x6000);
}
// BANK 5 (0x8000 - 0x9fff)
switch (m_mem_page) {
case 5:
case 10:
//window 2
space.unmap_write(0x8000, 0x9fff);
partner_window_2(5, 0, rom);
break;
case 8:
case 9:
//window 1
space.unmap_write(0x8000, 0x9fff);
partner_window_1(5, 0, rom);
break;
case 7:
membank("bank5")->set_base(ram + 0x0000);
break;
default:
membank("bank5")->set_base(ram + 0x8000);
break;
}
// BANK 6 (0xa000 - 0xb7ff)
switch (m_mem_page) {
case 5:
case 10:
//window 2
space.unmap_write(0xa000, 0xb7ff);
partner_window_2(6, 0, rom);
break;
case 6:
case 8:
//BASIC
space.unmap_write(0xa000, 0xb7ff);
membank("bank6")->set_base(rom + 0x12000); // BASIC
break;
case 7:
membank("bank6")->set_base(ram + 0x2000);
break;
default:
membank("bank6")->set_base(ram + 0xa000);
break;
}
// BANK 7 (0xb800 - 0xbfff)
switch (m_mem_page) {
case 4:
case 5:
case 10:
//window 2
space.unmap_write(0xb800, 0xbfff);
partner_window_2(7, 0x1800, rom);
break;
case 6:
case 8:
//BASIC
space.unmap_write(0xb800, 0xbfff);
membank("bank7")->set_base(rom + 0x13800); // BASIC
break;
case 7:
membank("bank7")->set_base(ram + 0x3800);
break;
default:
membank("bank7")->set_base(ram + 0xb800);
break;
}
// BANK 8 (0xc000 - 0xc7ff)
switch (m_mem_page) {
case 7:
membank("bank8")->set_base(ram + 0x4000);
break;
case 8:
case 10:
space.unmap_write(0xc000, 0xc7ff);
membank("bank8")->set_base(rom + 0x10000);
break;
default:
membank("bank8")->set_base(ram + 0xc000);
break;
}
// BANK 9 (0xc800 - 0xcfff)
switch (m_mem_page) {
case 7:
membank("bank9")->set_base(ram + 0x4800);
break;
case 8:
case 9:
// window 2
space.unmap_write(0xc800, 0xcfff);
partner_window_2(9, 0, rom);
break;
case 10:
space.unmap_write(0xc800, 0xcfff);
membank("bank9")->set_base(rom + 0x10800);
break;
default:
membank("bank9")->set_base(ram + 0xc800);
break;
}
// BANK 10 (0xd000 - 0xd7ff)
switch (m_mem_page) {
case 7:
membank("bank10")->set_base(ram + 0x5000);
break;
case 8:
case 9:
// window 2
space.unmap_write(0xd000, 0xd7ff);
partner_window_2(10, 0x0800, rom);
break;
default:
membank("bank10")->set_base(ram + 0xd000);
break;
}
// BANK 11 (0xdc00 - 0xddff)
partner_iomap_bank(rom);
// BANK 12 (0xe000 - 0xe7ff)
if (m_mem_page==1) {
membank("bank12")->set_base(rom + 0x10000);
} else {
//window 1
partner_window_1(12, 0, rom);
}
// BANK 13 (0xe800 - 0xffff)
switch (m_mem_page) {
case 3:
case 4:
case 5:
// window 1
partner_window_1(13, 0x800, rom);
break;
default:
// BIOS
membank("bank13")->set_base(rom + 0x10800);
break;
}
}
MACHINE_START_MEMBER(yunsun16_state, shocking)
{
machine_start();
membank("okibank")->configure_entries(0, 0x80000 / 0x20000, memregion("oki")->base(), 0x20000);
membank("okibank")->set_entry(0);
}
void queen_state::machine_reset()
{
membank("bios_bank")->set_base(memregion("bios")->base() + 0x30000);
membank("bios_ext")->set_base(memregion("bios")->base() + 0x20000);
}
void prestige_state::machine_start()
{
UINT8 *ram = m_ram->pointer();
memset(ram, 0x00, m_ram->size());
m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(prestige_state::prestige_int_ack),this));
membank("bank1")->configure_entries(0, 64, memregion("maincpu")->base(), 0x4000);
membank("bank2")->configure_entries(0, 64, memregion("maincpu")->base(), 0x4000);
membank("bank2")->configure_entries(64, 2, memregion("cart")->base(), 0x4000);
membank("bank3")->configure_entries(0, 64, memregion("maincpu")->base(), 0x4000);
membank("bank3")->configure_entries(64, 2, memregion("cart")->base(), 0x4000);
membank("bank4")->configure_entries(0, 4, ram, 0x2000);
membank("bank4")->configure_entries(4, 4, memregion("cart")->base(), 0x2000);
membank("bank5")->configure_entries(0, 4, ram, 0x2000);
membank("bank1")->set_entry(0);
membank("bank2")->set_entry(0);
membank("bank3")->set_entry(0);
membank("bank4")->set_entry(0);
membank("bank5")->set_entry(0);
//pointer to the videoram
m_vram = ram;
}
void xxmissio_state::machine_start()
{
membank("bank1")->configure_entries(0, 8, memregion("user1")->base(), 0x4000);
membank("bank1")->set_entry(0);
}
void newbrain_state::bankswitch()
{
address_space &program = m_maincpu->space(AS_PROGRAM);
int bank;
for (bank = 1; bank < 9; bank++)
{
UINT16 bank_start = (bank - 1) * 0x2000;
UINT16 bank_end = bank_start + 0x1fff;
char bank_name[10];
sprintf(bank_name,"bank%d",bank);
if (m_pwrup)
{
/* all banks point to ROM at 0xe000 */
memory_install_rom_helper(program, bank_name, bank_start, bank_end);
membank(bank_name)->configure_entry(0, memregion(Z80_TAG)->base() + 0xe000);
}
else
{
membank(bank_name)->configure_entry(0, memregion(Z80_TAG)->base() + bank_start);
if (bank < 5)
{
/* bank is RAM */
memory_install_ram_helper(program, bank_name, bank_start, bank_end);
}
else if (bank == 5)
{
/* 0x8000-0x9fff */
if (machine().root_device().memregion("eim")->base())
{
/* expansion interface ROM */
memory_install_rom_helper(program, bank_name, bank_start, bank_end);
membank(bank_name)->configure_entry(0, memregion("eim")->base() + 0x4000);
}
else
{
/* mirror of 0xa000-0xbfff */
if (machine().root_device().memregion(Z80_TAG)->base()[0xa001] == 0)
{
/* unmapped on the M model */
memory_install_unmapped(program, bank_name, bank_start, bank_end);
}
else
{
/* bank is ROM on the A model */
memory_install_rom_helper(program, bank_name, bank_start, bank_end);
}
membank(bank_name)->configure_entry(0, memregion(Z80_TAG)->base() + 0xa000);
}
}
else if (bank == 6)
{
/* 0xa000-0xbfff */
if (machine().root_device().memregion(Z80_TAG)->base()[0xa001] == 0)
{
/* unmapped on the M model */
memory_install_unmapped(program, bank_name, bank_start, bank_end);
}
else
{
/* bank is ROM on the A model */
memory_install_rom_helper(program, bank_name, bank_start, bank_end);
}
}
else
{
/* bank is ROM */
memory_install_rom_helper(program, bank_name, bank_start, bank_end);
}
}
membank(bank_name)->set_entry(0);
}
}
GFXDECODE_END
// The prom, the schematic, and the manual all contradict each other,
// so the colours can only be described as wild guesses. Further, the 38
// colour-load resistors are missing labels and values.
PALETTE_INIT_MEMBER( excali64_state, excali64 )
{
// do this here because driver_init hasn't run yet
m_p_videoram = memregion("videoram")->base();
m_p_hiresram = m_p_videoram + 0x2000;
uint8_t *main = memregion("roms")->base();
uint8_t *ram = memregion("rambank")->base();
// main ram (cp/m mode)
membank("bankr1")->configure_entry(0, &ram[0x0000]);
membank("bankr2")->configure_entry(0, &ram[0x2000]);
membank("bankr3")->configure_entry(0, &ram[0x3000]);
membank("bankr4")->configure_entry(0, &ram[0x4000]);//boot
membank("bankw1")->configure_entry(0, &ram[0x0000]);//boot
membank("bankw2")->configure_entry(0, &ram[0x2000]);
membank("bankw3")->configure_entry(0, &ram[0x3000]);
membank("bankw4")->configure_entry(0, &ram[0x4000]);//boot
// rom_1
membank("bankr1")->configure_entry(1, &main[0x0000]);//boot
membank("bankr1")->configure_entry(2, &main[0x2000]);
// rom_2
membank("bankr2")->configure_entry(1, &main[0x4000]);//boot
membank("bankr3")->configure_entry(1, &main[0x5000]);//boot
// videoram
membank("bankr2")->configure_entry(2, &m_p_videoram[0x0000]);
membank("bankw2")->configure_entry(2, &m_p_videoram[0x0000]);//boot
// hiresram
membank("bankr3")->configure_entry(2, &m_p_videoram[0x1000]);
membank("bankw3")->configure_entry(2, &m_p_videoram[0x1000]);//boot
membank("bankr4")->configure_entry(2, &m_p_hiresram[0x0000]);
membank("bankw4")->configure_entry(2, &m_p_hiresram[0x0000]);
// Set up foreground colours
uint8_t r,g,b,i,code;
for (i = 0; i < 32; i++)
{
code = m_p_chargen[0x1000+i];
r = (BIT(code, 0) ? 38 : 0) + (BIT(code, 1) ? 73 : 0) + (BIT(code, 2) ? 144 : 0);
b = (BIT(code, 3) ? 38 : 0) + (BIT(code, 4) ? 73 : 0) + (BIT(code, 5) ? 144 : 0);
g = (BIT(code, 6) ? 85 : 0) + (BIT(code, 7) ? 170 : 0);
palette.set_pen_color(i, r, g, b);
}
// Background
palette.set_pen_color(32, 0x00, 0x00, 0x00); // 0 Black
palette.set_pen_color(33, 0xff, 0x00, 0x00); // 1 Red
palette.set_pen_color(34, 0x00, 0x00, 0xff); // 2 Blue
palette.set_pen_color(35, 0xff, 0x00, 0xff); // 3 Magenta
palette.set_pen_color(36, 0x00, 0xff, 0x00); // 4 Green
palette.set_pen_color(37, 0xff, 0xff, 0x00); // 5 Yellow
palette.set_pen_color(38, 0x00, 0xff, 0xff); // 6 Cyan
palette.set_pen_color(39, 0xff, 0xff, 0xff); // 7 White
}
void xmen_state::sound_reset_bank()
{
membank("bank4")->set_entry(m_sound_curbank & 0x07);
}
void niyanpai_state::niyanpai_soundbank_w(int data)
{
UINT8 *SNDROM = memregion("audiocpu")->base();
membank("bank1")->set_base(&SNDROM[0x08000 + (0x8000 * (data & 0x03))]);
}
void taotaido_state::machine_start()
{
membank("soundbank")->configure_entries(0, 4, memregion("audiocpu")->base(), 0x8000);
save_item(NAME(m_pending_command));
}
//AM_RANGE(0177770, 0177771) // read/write
ADDRESS_MAP_END
WRITE16_MEMBER(ms0515_state::ms0515_bank_w)
{
UINT8 *ram = machine().device<ram_device>(RAM_TAG)->pointer();
membank("bank0")->set_base(ram + 0000000 + BIT(data,0) * 0160000);
membank("bank1")->set_base(ram + 0020000 + BIT(data,1) * 0160000);
membank("bank2")->set_base(ram + 0040000 + BIT(data,2) * 0160000);
membank("bank3")->set_base(ram + 0060000 + BIT(data,3) * 0160000);
membank("bank4")->set_base(ram + 0100000 + BIT(data,4) * 0160000);
membank("bank5")->set_base(ram + 0120000 + BIT(data,5) * 0160000);
membank("bank6")->set_base(ram + 0140000 + BIT(data,6) * 0160000);
if (BIT(data,7)) {
switch((data >> 10) % 3)
{
case 0: // 000000 - 037777
membank("bank0")->set_base(ram + 0000000 + 0340000);
membank("bank1")->set_base(ram + 0020000 + 0340000);
break;
case 1: // 040000 - 077777
membank("bank2")->set_base(ram + 0000000 + 0340000);
membank("bank3")->set_base(ram + 0020000 + 0340000);
break;
case 2:
case 3: // 100000 - 137777
membank("bank4")->set_base(ram + 0000000 + 0340000);
membank("bank5")->set_base(ram + 0020000 + 0340000);
break;
}
}
}
void dai_state::dai_update_memory(int dai_rom_bank)
{
membank("bank2")->set_entry(dai_rom_bank);
}
void xor100_state::bankswitch()
{
address_space &program = m_maincpu->space(AS_PROGRAM);
int banks = m_ram->size() / 0x10000;
switch (m_mode)
{
case EPROM_0000:
if (m_bank < banks)
{
program.install_write_bank(0x0000, 0xffff, "bank1");
membank("bank1")->set_entry(1 + m_bank);
}
else
{
program.unmap_write(0x0000, 0xffff);
}
program.install_read_bank(0x0000, 0xf7ff, 0x07ff, 0, "bank2");
program.install_read_bank(0xf800, 0xffff, "bank3");
membank("bank2")->set_entry(0);
membank("bank3")->set_entry(0);
break;
case EPROM_F800:
if (m_bank < banks)
{
program.install_write_bank(0x0000, 0xffff, "bank1");
program.install_read_bank(0x0000, 0xf7ff, "bank2");
membank("bank1")->set_entry(1 + m_bank);
membank("bank2")->set_entry(1 + m_bank);
}
else
{
program.unmap_write(0x0000, 0xffff);
program.unmap_read(0x0000, 0xf7ff);
}
program.install_read_bank(0xf800, 0xffff, "bank3");
membank("bank3")->set_entry(0);
break;
case EPROM_OFF:
if (m_bank < banks)
{
program.install_write_bank(0x0000, 0xffff, "bank1");
program.install_read_bank(0x0000, 0xf7ff, "bank2");
program.install_read_bank(0xf800, 0xffff, "bank3");
membank("bank1")->set_entry(1 + m_bank);
membank("bank2")->set_entry(1 + m_bank);
membank("bank3")->set_entry(1 + m_bank);
}
else
{
program.unmap_write(0x0000, 0xffff);
program.unmap_read(0x0000, 0xf7ff);
program.unmap_read(0xf800, 0xffff);
}
break;
}
}
void dai_state::machine_reset()
{
membank("bank1")->set_base(m_ram->pointer());
}
MACHINE_RESET_MEMBER(yunsun16_state, shocking)
{
machine_reset();
membank("okibank")->set_entry(0);
}
void savquest_state::mtxc_config_w(int function, int reg, uint8_t data)
{
// osd_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine().describe_context().c_str(), function, reg, data);
#if 1
switch(reg)
{
case 0x59: // PAM0
{
if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
{
membank("bios_f0000")->set_base(m_bios_f0000_ram.get());
}
else // disable RAM access (reads go to BIOS ROM)
{
membank("bios_f0000")->set_base(memregion("bios")->base() + 0x30000);
}
break;
}
case 0x5e: // PAM5
{
if (data & 0x10) // enable RAM access to region 0xe4000 - 0xe7fff
{
membank("bios_e4000")->set_base(m_bios_e4000_ram.get());
}
else // disable RAM access (reads go to BIOS ROM)
{
membank("bios_e4000")->set_base(memregion("bios")->base() + 0x24000);
}
if (data & 1) // enable RAM access to region 0xe0000 - 0xe3fff
{
membank("bios_e0000")->set_base(m_bios_e0000_ram.get());
}
else // disable RAM access (reads go to BIOS ROM)
{
membank("bios_e0000")->set_base(memregion("bios")->base() + 0x20000);
}
break;
}
case 0x5f: // PAM6
{
if (data & 0x10) // enable RAM access to region 0xec000 - 0xeffff
{
membank("bios_ec000")->set_base(m_bios_ec000_ram.get());
}
else // disable RAM access (reads go to BIOS ROM)
{
membank("bios_ec000")->set_base(memregion("bios")->base() + 0x2c000);
}
if (data & 1) // enable RAM access to region 0xe8000 - 0xebfff
{
membank("bios_e8000")->set_base(m_bios_e8000_ram.get());
}
else // disable RAM access (reads go to BIOS ROM)
{
membank("bios_e8000")->set_base(memregion("bios")->base() + 0x28000);
}
break;
}
}
#endif
m_mtxc_config_reg[reg] = data;
}
void argo_state::machine_reset()
{
membank("boot")->set_entry(1);
timer_set(attotime::from_usec(5), TIMER_BOOT);
}
GFXDECODE_END
void quizdna_state::machine_start()
{
membank("mainbank")->configure_entries(0, 64, memregion("maincpu")->base() + 0x10000, 0x4000);
}
void calchase_state::machine_reset()
{
//membank("bank1")->set_base(memregion("bios")->base() + 0x10000);
membank("bios_bank")->set_base(memregion("bios")->base() + 0x10000);
membank("bios_ext")->set_base(memregion("bios")->base() + 0);
}
void tvc_state::set_mem_page(UINT8 data)
{
address_space &space = m_maincpu->space(AS_PROGRAM);
switch (data & 0x18)
{
case 0x00 : // system ROM selected
TVC_INSTALL_ROM_BANK(0, "bank1", 0x0000, 0x3fff);
membank("bank1")->set_base(m_bios_rom->base());
break;
case 0x08 : // Cart ROM selected
if (m_cart_rom)
{
TVC_INSTALL_ROM_BANK(0, "bank1", 0x0000, 0x3fff);
membank("bank1")->set_base(m_cart_rom->base());
}
break;
case 0x10 : // RAM selected
TVC_INSTALL_RAM_BANK(0, "bank1", 0x0000, 0x3fff);
membank("bank1")->set_base(m_ram->pointer());
break;
case 0x18 : // Video RAM
if (m_vram->bytes() > 0x4000)
{
// TVC 64+ only
TVC_INSTALL_RAM_BANK(0, "bank1", 0x0000, 0x3fff);
membank("bank1")->set_base(m_vram->base() + ((m_vram_bank & 0x03)<<14));
}
else
{
space.unmap_readwrite(0x0000, 0x3fff);
m_bank_type[0] = -1;
}
break;
}
if ((data & 0x20)==0) // Video RAM
{
TVC_INSTALL_RAM_BANK(2, "bank3", 0x8000, 0xbfff);
membank("bank3")->set_base(m_vram->base() + ((m_vram_bank & 0x0c)<<12));
}
else // System RAM page 3
{
if (m_ram->size() > 0x8000)
{
TVC_INSTALL_RAM_BANK(2, "bank3", 0x8000, 0xbfff);
membank("bank3")->set_base(m_ram->pointer() + 0x8000);
}
else
{
space.unmap_readwrite(0x8000, 0xbfff);
m_bank_type[2] = -1;
}
}
switch(data & 0xc0)
{
case 0x00 : // Cart ROM selected
if (m_cart_rom)
{
TVC_INSTALL_ROM_BANK(3, "bank4", 0xc000, 0xffff);
membank("bank4")->set_base(m_cart_rom->base());
}
break;
case 0x40 : // System ROM selected
TVC_INSTALL_ROM_BANK(3, "bank4", 0xc000, 0xffff);
membank("bank4")->set_base(m_bios_rom->base());
break;
case 0x80 : // RAM selected
if (m_ram->size() > 0x8000)
{
TVC_INSTALL_RAM_BANK(3, "bank4", 0xc000, 0xffff);
membank("bank4")->set_base(m_ram->pointer() + 0xc000);
}
else
{
space.unmap_readwrite(0xc000, 0xffff);
m_bank_type[3] = -1;
}
break;
case 0xc0 : // External ROM selected
TVC_INSTALL_ROM_BANK(3, "bank4", 0xc000, 0xffff);
membank("bank4")->set_base(m_ext->base());
space.install_readwrite_handler (0xc000, 0xdfff, 0, 0, read8_delegate(FUNC(tvc_state::expansion_r), this), write8_delegate(FUNC(tvc_state::expansion_w), this), 0);
m_bank_type[3] = -1;
break;
}
}
void cgenie_state::machine_reset()
{
address_space &space = m_maincpu->space(AS_PROGRAM);
UINT8 *ROM = memregion("maincpu")->base();
/* reset the AY8910 to be quiet, since the cgenie BIOS doesn't */
AYWriteReg(0, 0, 0);
AYWriteReg(0, 1, 0);
AYWriteReg(0, 2, 0);
AYWriteReg(0, 3, 0);
AYWriteReg(0, 4, 0);
AYWriteReg(0, 5, 0);
AYWriteReg(0, 6, 0);
AYWriteReg(0, 7, 0x3f);
AYWriteReg(0, 8, 0);
AYWriteReg(0, 9, 0);
AYWriteReg(0, 10, 0);
/* wipe out color RAM */
memset(&ROM[0x0f000], 0x00, 0x0400);
/* wipe out font RAM */
memset(&ROM[0x0f400], 0xff, 0x0400);
if( ioport("DSW0")->read() & 0x80 )
{
logerror("cgenie floppy discs enabled\n");
}
else
{
logerror("cgenie floppy discs disabled\n");
}
/* copy DOS ROM, if enabled or wipe out that memory area */
if( ioport("DSW0")->read() & 0x40 )
{
if ( ioport("DSW0")->read() & 0x80 )
{
space.install_read_bank(0xc000, 0xdfff, "bank10");
space.nop_write(0xc000, 0xdfff);
membank("bank10")->set_base(&ROM[0x0c000]);
logerror("cgenie DOS enabled\n");
memcpy(&ROM[0x0c000],&ROM[0x10000], 0x2000);
}
else
{
space.nop_readwrite(0xc000, 0xdfff);
logerror("cgenie DOS disabled (no floppy image given)\n");
}
}
else
{
space.nop_readwrite(0xc000, 0xdfff);
logerror("cgenie DOS disabled\n");
memset(&memregion("maincpu")->base()[0x0c000], 0x00, 0x2000);
}
/* copy EXT ROM, if enabled or wipe out that memory area */
if (ioport("DSW0")->read() & 0x20 && m_cart->exists())
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0xe000, 0xefff, read8_delegate(FUNC(generic_slot_device::read_rom),(generic_slot_device*)m_cart));
logerror("cgenie EXT enabled\n");
}
else
{
space.nop_readwrite(0xe000, 0xefff);
logerror("cgenie EXT disabled\n");
}
m_cass_level = 0;
m_cass_bit = 1;
}
void sf7000_state::machine_reset()
{
membank("bank1")->set_entry(0);
membank("bank2")->set_entry(0);
}
void mc1000_state::machine_reset()
{
membank("bank1")->set_entry(1);
m_rom0000 = 1;
}
/*
macs.c - Multi Amenity Cassette System
processor seems to be ST0016 (z80 based) from SETA
around 0x3700 of the bios (when interleaved) contains the ram test text
TODO:
(general)
-Hook-Up bios.
(yujan)
-Girls disappears when you win.
-Some gfx are offset.
----- Game Notes -----
Kisekae Mahjong (c)1995 I'MAX
Kisekae Hanafuda (c)1995 I'MAX
Seimei-Kantei-Meimei-Ki Cult Name (c)1996 I'MAX
KISEKAE -- info
* DIP SWITCH *
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
-------------------------------------------------------
P2 Level | Normal |off|off| |
| Weak |on |off| |
| Strong |off|on | |
|Very strong|on |on | |
-------------------------------------------------------
P2 Points| Normal | |off|off| |
| Easy | |on |off| |
| Hard | |off|on | |
| Very hard | |on |on | |
-------------------------------------------------------
P1 | 1000pts | |off| |
points | 2000pts | |on | |
-------------------------------------------------------
Auto | Yes | |off| |
tumo | No | |on | |
-------------------------------------------------------
Not | | |off| |
Used | | |on | |
-------------------------------------------------------
Tumo | Long | |off|
time | Short | |on |
-------------------------------------------------------
* at slotA -> DIP SW3
slotB -> DIP SW4
*/
#include "emu.h"
#include "cpu/z80/z80.h"
#include "sound/st0016.h"
#include "includes/st0016.h"
class macs_state : public st0016_state
{
public:
macs_state(const machine_config &mconfig, device_type type, const char *tag)
: st0016_state(mconfig, type, tag),
m_ram2(*this, "ram2") { }
UINT8 m_mux_data;
UINT8 m_rev;
UINT8 *m_ram1;
required_shared_ptr<UINT8> m_ram2;
DECLARE_WRITE8_MEMBER(rambank_w);
DECLARE_READ8_MEMBER(macs_input_r);
DECLARE_WRITE8_MEMBER(macs_rom_bank_w);
DECLARE_WRITE8_MEMBER(macs_output_w);
DECLARE_DRIVER_INIT(macs);
DECLARE_DRIVER_INIT(kisekaeh);
DECLARE_DRIVER_INIT(kisekaem);
DECLARE_DRIVER_INIT(macs2);
DECLARE_MACHINE_RESET(macs);
};
static ADDRESS_MAP_START( macs_mem, AS_PROGRAM, 8, macs_state )
AM_RANGE(0x0000, 0x7fff) AM_ROMBANK("bank4")
AM_RANGE(0x8000, 0xbfff) AM_ROMBANK("bank1")
AM_RANGE(0xc000, 0xcfff) AM_READ(st0016_sprite_ram_r) AM_WRITE(st0016_sprite_ram_w)
AM_RANGE(0xd000, 0xdfff) AM_READ(st0016_sprite2_ram_r) AM_WRITE(st0016_sprite2_ram_w)
AM_RANGE(0xe000, 0xe7ff) AM_RAM /* work ram ? */
AM_RANGE(0xe800, 0xe87f) AM_RAM AM_SHARE("ram2")
AM_RANGE(0xe900, 0xe9ff) AM_DEVREADWRITE("stsnd", st0016_device, st0016_snd_r, st0016_snd_w)
AM_RANGE(0xea00, 0xebff) AM_READ(st0016_palette_ram_r) AM_WRITE(st0016_palette_ram_w)
AM_RANGE(0xec00, 0xec1f) AM_READ(st0016_character_ram_r) AM_WRITE(st0016_character_ram_w)
AM_RANGE(0xf000, 0xf7ff) AM_RAMBANK("bank3") /* common /backup ram ?*/
AM_RANGE(0xf800, 0xffff) AM_RAMBANK("bank2") /* common /backup ram ?*/
ADDRESS_MAP_END
WRITE8_MEMBER(macs_state::rambank_w)
{
membank("bank3")->set_base(&m_ram1[0x10000+(data&1)*0x800] );
}
void lc80_state::machine_start()
{
address_space &program = m_maincpu->space(AS_PROGRAM);
UINT8 *ROM = memregion(Z80_TAG)->base();
/* setup memory banking */
membank("bank1")->configure_entry(0, &ROM[0]); // TODO
membank("bank1")->configure_entry(1, &ROM[0]);
membank("bank1")->set_entry(1);
membank("bank2")->configure_entry(0, &ROM[0x800]); // TODO
membank("bank2")->configure_entry(1, &ROM[0x800]);
membank("bank2")->set_entry(1);
membank("bank3")->configure_entry(0, &ROM[0x1000]); // TODO
membank("bank3")->configure_entry(1, &ROM[0x1000]);
membank("bank3")->set_entry(1);
membank("bank4")->configure_entry(0, &ROM[0x2000]);
membank("bank4")->set_entry(0);
program.install_readwrite_bank(0x0000, 0x07ff, "bank1");
program.install_readwrite_bank(0x0800, 0x0fff, "bank2");
program.install_readwrite_bank(0x1000, 0x17ff, "bank3");
switch (m_ram->size())
{
case 1*1024:
program.install_readwrite_bank(0x2000, 0x23ff, "bank4");
program.unmap_readwrite(0x2400, 0x2fff);
break;
case 2*1024:
program.install_readwrite_bank(0x2000, 0x27ff, "bank4");
program.unmap_readwrite(0x2800, 0x2fff);
break;
case 3*1024:
program.install_readwrite_bank(0x2000, 0x2bff, "bank4");
program.unmap_readwrite(0x2c00, 0x2fff);
break;
case 4*1024:
program.install_readwrite_bank(0x2000, 0x2fff, "bank4");
break;
}
/* register for state saving */
save_item(NAME(m_digit));
save_item(NAME(m_segment));
}
void plan80_state::machine_reset()
{
membank("boot")->set_entry(1);
machine().scheduler().timer_set(attotime::from_usec(10), timer_expired_delegate(FUNC(plan80_state::plan80_boot),this));
}