static WRITE8_HANDLER( pc_dma_write_byte )
{
offs_t page_offset = (((offs_t) dma_offset[0][dma_channel]) << 16)
& 0xFF0000;
memory_write_byte(space, page_offset + offset, data);
}
static void galpani2_write_kaneko(running_device *device)
{
const address_space *dstspace = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
int i,x,tpattidx;
unsigned char testpattern[] = {0xFF,0x55,0xAA,0xDD,0xBB,0x99};
/* Write "KANEKO" to 100000-100005, but do not clash with ram test */
x = 0;
for (i = 0x100000; i < 0x100007; i++)
{
for (tpattidx = 0; tpattidx < 6; tpattidx++)
{
if (memory_read_byte(dstspace,i) == testpattern[tpattidx]) x = 1; //ram test fragment present
}
}
if ( x == 0 )
{
memory_write_byte(dstspace,0x100000,0x4b); //K
memory_write_byte(dstspace,0x100001,0x41); //A
memory_write_byte(dstspace,0x100002,0x4e); //N
memory_write_byte(dstspace,0x100003,0x45); //E
memory_write_byte(dstspace,0x100004,0x4b); //K
memory_write_byte(dstspace,0x100005,0x4f); //O
}
}
INLINE void WRITE8(hc11_state *cpustate, UINT32 address, UINT8 value)
{
if(address >= cpustate->reg_position && address < cpustate->reg_position+(cpustate->has_extended_io ? 0x100 : 0x40))
{
hc11_regs_w(cpustate, address, value);
return;
}
else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size)
{
cpustate->internal_ram[address-cpustate->ram_position] = value;
return;
}
memory_write_byte(cpustate->program, address, value);
}
static WRITE8_HANDLER( galpani2_mcu_init_w )
{
running_machine *machine = space->machine;
const address_space *srcspace = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
const address_space *dstspace = cputag_get_address_space(machine, "sub", ADDRESS_SPACE_PROGRAM);
UINT32 mcu_address, mcu_data;
for ( mcu_address = 0x100010; mcu_address < (0x100010 + 6); mcu_address += 1 )
{
mcu_data = memory_read_byte(srcspace, mcu_address );
memory_write_byte(dstspace, mcu_address-0x10, mcu_data);
}
cputag_set_input_line(machine, "sub", INPUT_LINE_IRQ7, HOLD_LINE); //MCU Initialised
}
/*===========================================================
* This ftn outputs a byte via the SPI controller. Any
* other CSx or IOMUX is handled elsewhere.
*==========================================================*/
void spi_output_byte( u8 *dbuf, int bytes )
{
u8 tmp, cnt;
if (spi_base == 0)
spi_init_address();
/* check for idle */
while (1) {
if ( memory_read_byte(spi_base + SPI_CNTRL0_3) & SPI_STATUS_BUSY)
printf("SPI controller BUSY\n");
else
break;
}
/* clear the FIFO pointer */
memory_write_byte(spi_base + SPI_CNTRL0_2, memory_read_byte(spi_base + SPI_CNTRL0_2) | SPI_FIFO_PTR_CLR);
/* read the FIFO pointer */
tmp = memory_read_byte(spi_base + SPI_CNTRL1_D) & SPI_FIFO_PTR_MASK;
if (tmp != 0)
printf("ERROR: FIFO PTR is %d should be 0\n",tmp);
/* write the TX/RX byte counters */
memory_write_byte(spi_base + SPI_CNTRL0_1, bytes - 1);
/* write the 1st byte of data to the OPCODE reg */
memory_write_byte(spi_base + SPI_CNTRL0_0, *(dbuf + 0) );
if ( bytes > 8 )
printf("ERROR: too many bytes specified [%d]\n",bytes);
if (bytes > 1) {
for ( cnt = 1; cnt < bytes; cnt++ )
memory_write_byte(spi_base + SPI_CNTRL1_C, *(dbuf + cnt) );
}
/* read the FIFO pointer */
tmp = memory_read_byte(spi_base + SPI_CNTRL1_D) & SPI_FIFO_PTR_MASK;
if ((tmp + 1 ) != bytes)
printf("ERROR: FIFO PTR is %d should be %d\n",tmp,bytes);
/* clear the FIFO pointer */
memory_write_byte(spi_base + SPI_CNTRL0_2, memory_read_byte(spi_base + SPI_CNTRL0_2) | SPI_FIFO_PTR_CLR);
/* Start the SPI cycle */
memory_write_byte(spi_base + SPI_CNTRL0_2, memory_read_byte(spi_base + SPI_CNTRL0_2) | SPI_TRANSMIT );
}
static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
{
int reg = address & 0xff;
switch(reg)
{
case 0x00: /* PORTA */
memory_write_byte(cpustate->io, MC68HC11_IO_PORTA, value);
return;
case 0x01: /* DDRA */
//mame_printf_debug("HC11: ddra = %02X\n", value);
return;
case 0x03: /* PORTC */
memory_write_byte(cpustate->io, MC68HC11_IO_PORTC, value);
return;
case 0x04: /* PORTC */
memory_write_byte(cpustate->io, MC68HC11_IO_PORTB, value);
return;
case 0x08: /* PORTD */
memory_write_byte(cpustate->io, MC68HC11_IO_PORTD, value); //mask & 0x3f?
return;
case 0x09: /* DDRD */
//mame_printf_debug("HC11: ddrd = %02X\n", value);
return;
case 0x0a: /* PORTE */
memory_write_byte(cpustate->io, MC68HC11_IO_PORTE, value);
return;
case 0x22: /* TMSK1 */
return;
case 0x23:
cpustate->tflg1 = value;
return;
case 0x24: /* TMSK2 */
return;
case 0x28: /* SPCR1 */
return;
case 0x30: /* ADCTL */
cpustate->adctl = value;
return;
case 0x38: /* OPT2 */
return;
case 0x39: /* OPTION */
return;
case 0x3a: /* COPRST (watchdog) */
return;
case 0x3d: /* INIT */
{
int reg_page = value & 0xf;
int ram_page = (value >> 4) & 0xf;
if (reg_page == ram_page) {
cpustate->reg_position = reg_page << 12;
cpustate->ram_position = (ram_page << 12) + 0x100;
} else {
cpustate->reg_position = reg_page << 12;
cpustate->ram_position = ram_page << 12;
}
return;
}
case 0x3f: /* CONFIG */
return;
case 0x70: /* SCBDH */
return;
case 0x71: /* SCBDL */
return;
case 0x72: /* SCCR1 */
return;
case 0x73: /* SCCR2 */
return;
case 0x77: /* SCDRL */
return;
case 0x7c: /* PORTH */
memory_write_byte(cpustate->io, MC68HC11_IO_PORTH, value);
return;
case 0x7d: /* DDRH */
//mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, cpustate->pc);
return;
case 0x7e: /* PORTG */
memory_write_byte(cpustate->io, MC68HC11_IO_PORTG, value);
return;
case 0x7f: /* DDRG */
//mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, cpustate->pc);
return;
case 0x88: /* SPCR2 */
return;
case 0x89: /* SPSR2 */
return;
case 0x8a: /* SPDR2 */
memory_write_byte(cpustate->io, MC68HC11_IO_SPI2_DATA, value);
return;
case 0x8b: /* OPT4 */
return;
}
logerror("HC11: regs_w %02X, %02X\n", reg, value);
}
static void galpani2_mcu_nmi1(running_machine *machine)
{
const address_space *srcspace = cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM);
const address_space *dstspace = cputag_get_address_space(machine, "sub", ADDRESS_SPACE_PROGRAM);
UINT32 mcu_list, mcu_command, mcu_address, mcu_extra, mcu_src, mcu_dst, mcu_size;
for ( mcu_list = 0x100021; mcu_list < (0x100021 + 0x40); mcu_list += 4 )
{
mcu_command = memory_read_byte(srcspace, mcu_list);
mcu_address = 0x100000 +
(memory_read_byte(srcspace, mcu_list + 1)<<8) +
(memory_read_byte(srcspace, mcu_list + 2)<<0) ;
mcu_extra = memory_read_byte(srcspace, mcu_list + 3); //0xff for command $A and $2, 0x02 for others
if (mcu_command != 0)
{
logerror("%s : MCU [$%06X] endidx = $%02X / command = $%02X addr = $%04X ? = $%02X.\n",
cpuexec_describe_context(machine),
mcu_list,
memory_read_byte(srcspace, 0x100020),
mcu_command,
mcu_address,
mcu_extra
);
}
switch (mcu_command)
{
case 0x00:
break;
case 0x02: //Copy N bytes from RAM2 to RAM1?, gp2se is the only one to use it, often!
mcu_src = (memory_read_byte(srcspace, mcu_address + 2)<<8) +
(memory_read_byte(srcspace, mcu_address + 3)<<0) ;
mcu_dst = (memory_read_byte(srcspace, mcu_address + 6)<<8) +
(memory_read_byte(srcspace, mcu_address + 7)<<0) ;
mcu_size = (memory_read_byte(srcspace, mcu_address + 8)<<8) +
(memory_read_byte(srcspace, mcu_address + 9)<<0) ;
logerror("%s : MCU executes command $%02X, %04X %02X-> %04x\n",cpuexec_describe_context(machine),mcu_command,mcu_src,mcu_size,mcu_dst);
for( ; mcu_size > 0 ; mcu_size-- )
{
mcu_src &= 0xffff; mcu_dst &= 0xffff;
memory_write_byte(srcspace,0x100000 + mcu_dst,memory_read_byte(dstspace,0x100000 + mcu_src));
mcu_src ++; mcu_dst ++;
}
/* Raise a "job done" flag */
memory_write_byte(srcspace,mcu_address+0,0xff);
memory_write_byte(srcspace,mcu_address+1,0xff);
break;
case 0x0a: // Copy N bytes from RAM1 to RAM2
mcu_src = (memory_read_byte(srcspace, mcu_address + 2)<<8) +
(memory_read_byte(srcspace, mcu_address + 3)<<0) ;
mcu_dst = (memory_read_byte(srcspace, mcu_address + 6)<<8) +
(memory_read_byte(srcspace, mcu_address + 7)<<0) ;
mcu_size = (memory_read_byte(srcspace, mcu_address + 8)<<8) +
(memory_read_byte(srcspace, mcu_address + 9)<<0) ;
logerror("%s : MCU executes command $%02X, %04X %02X-> %04x\n",cpuexec_describe_context(machine),mcu_command,mcu_src,mcu_size,mcu_dst);
for( ; mcu_size > 0 ; mcu_size-- )
{
mcu_src &= 0xffff; mcu_dst &= 0xffff;
memory_write_byte(dstspace,0x100000 + mcu_dst,memory_read_byte(srcspace,0x100000 + mcu_src));
mcu_src ++; mcu_dst ++;
}
/* Raise a "job done" flag */
memory_write_byte(srcspace,mcu_address+0,0xff);
memory_write_byte(srcspace,mcu_address+1,0xff);
break;
//case 0x10: //? Clear gal?
//case 0x14: //? Display gal?
//until
//case 0x50: //? Display gal?
//case 0x68: //? Display "Changed" monster?
//until
//case 0x6E: //? Display "Changed" monster?
//case 0x85: //? Do what?
default:
/* Raise a "job done" flag */
memory_write_byte(srcspace,mcu_address+0,0xff);
memory_write_byte(srcspace,mcu_address+1,0xff);
logerror("%s : MCU ERROR, unknown command $%02X\n",cpuexec_describe_context(machine),mcu_command);
}
/* Erase command (so that it won't be processed again)? */
memory_write_byte(srcspace,mcu_list,0x00);
}
}
void spi_write_reg( u8 reg, u8 data ) {
if (spi_base == 0)
spi_init_address();
memory_write_byte(spi_base + reg, data );
}
