/**
* Enable Exceptions.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void Xil_ExceptionEnable(void)
{
#ifdef MICROBLAZE_EXCEPTIONS_ENABLED
microblaze_enable_exceptions();
#endif
microblaze_enable_interrupts();
}
// DO NOT MODIFY THE CODE BELOW
int w3_node_init() {
int status;
int ret = XST_SUCCESS;
microblaze_enable_exceptions();
//Initialize the AD9512 clock buffers (RF reference and sampling clocks)
status = clk_init(CLK_BASEADDR, 2);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in clk_init (%d)\n", status);
ret = XST_FAILURE;
}
status = clk_config_dividers (CLK_BASEADDR, 2, CLK_SAMP_OUTSEL_AD_RFA);
if(status != XST_SUCCESS) {
xil_printf("wclk_config_dividers (%d)\n", status);
ret = XST_FAILURE;
}
//Initialize the AD9963 ADCs/DACs for on-board RF interfaces
ad_init(AD_BASEADDR, (RFA_AD_CS | RFB_AD_CS), 2);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in ad_init (%d)\n", status);
ret = XST_FAILURE;
}
//Initialize the radio_controller core and MAX2829 transceivers for on-board RF interfaces
status = radio_controller_init(RC_BASEADDR, (RC_RFA | RC_RFB), 1, 1);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in radioController_initialize (%d)\n", status);
ret = XST_FAILURE;
}
return ret;
}
void start_intc(void) {
// Setting Interupt controller
xil_printf("\r\nSetting up Interrupt Controller:\r\n");
//Initialize exception handling
xil_printf(" Initialize exception handling\r\n");
microblaze_enable_exceptions();
// Register external interrupt handler
xil_printf(" Register external interrupt handler\r\n");
microblaze_register_handler((XInterruptHandler)XIntc_DeviceInterruptHandler,
(void *)XPAR_XPS_INTC_0_DEVICE_ID);
// // Register UART interrupt handler
// // xil_printf(" Register UART interrupt handler\r\n");
// XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,XPAR_INTC_0_RS232_INTERRUPT_INTR,
// (XInterruptHandler)uart_int_handler,(void *)XPAR_RS232_BASEADDR);
// Register OPB_FX2 interrupt handler
xil_printf(" Register I2C_SLAVE interrupt handler\r\n");
XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,XPAR_XPS_INTC_0_XPS_I2C_SLAVE_0_IP2INTC_IRPT_INTR,
(XInterruptHandler)i2c_slave_int_handler,(void *)XPAR_XPS_I2C_SLAVE_0_BASEADDR);
// Enable timer interrupts
// // xil_printf(" Register OPB_TIMER interrupt handler\r\n");
// XIntc_mMasterEnable(XPAR_OPB_TIMER_0_BASEADDR); // Start the interrupt controller
// XIntc_SetIntrSvcOption( XPAR_INTC_0_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
// Enable uart interrupt in the interrupt controller
xil_printf(" Enable interrupts in the interrupt controller\r\n");
XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
// XPAR_RS232_INTERRUPT_MASK |
// XPAR_XPS_TIMER_0_INTERRUPT_MASK |
// XPAR_OPB_FX2_0_INTERRUPT_MASK |
XPAR_XPS_I2C_SLAVE_0_IP2INTC_IRPT_MASK);
xil_printf(" Start the interrupt controller\r\n");
XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
// Enable uart interrupts
// // xil_printf(" Enable uart interrupt in Uartlite\r\n");
// XUartLite_mEnableIntr(XPAR_RS232_BASEADDR);
// xil_printf(" Enable all interrupts in XPS_FX2\r\n");
// Enable MB interrupts
// xil_printf(" Enable MB interrupts\r\n");
microblaze_enable_interrupts();
}
void vPortExceptionsInstallHandlers( void )
{
static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
if( ulHandlersAlreadyInstalled == pdFALSE )
{
ulHandlersAlreadyInstalled = pdTRUE;
#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
microblaze_enable_exceptions();
}
}
int w3_node_init() {
int status;
u8 CMswitch;
XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
int ret = XST_SUCCESS;
microblaze_enable_exceptions();
//Initialize the AD9512 clock buffers (RF reference and sampling clocks)
CMswitch = clk_config_read_clkmod_status(CLK_BASEADDR);
status = clk_init(CLK_BASEADDR, 2);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in clk_init (%d)\n", status);
ret = XST_FAILURE;
}
//Configure this node's clock inputs and outputs, based on the state of the CM-MMCX switch
// If no CM-MMCX is present, CMswitch will read as 0x3 (on-board clock sources, off-board outputs disabled)
switch(CMswitch){
// RF | Sample | Outputs
case 0x0: // Off-Board | Off-Board | Off
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_CLKMOD);
xil_printf("\nClock config %d:\n RF: Off-board\n Samp: Off-board\n Off-board Outputs: Disabled\n\n", CMswitch);
break;
case 0x1: // Off-Board | On-Board | Off
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_CLKMOD);
xil_printf("\nClock config %d:\n RF: Off-board\n Samp: On-board\n Off-board Outputs: Disabled\n\n", CMswitch);
break;
case 0x2: // On-Board | On-Board | On
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
clk_config_dividers(CLK_BASEADDR, 1, CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR);
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_ONBOARD);
xil_printf("\nClock config %d:\n RF: On-board\n Samp: On-board\n Off-board Outputs: Enabled\n\n", CMswitch);
break;
case 0x3: // On-Board | On-Board | Off
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_OFF, (CLK_SAMP_OUTSEL_CLKMODHDR | CLK_RFREF_OUTSEL_CLKMODHDR));
clk_config_input_rf_ref(CLK_BASEADDR, CLK_INSEL_ONBOARD);
//xil_printf("\nClock config %d:\n RF: On-board\n Samp: On-board\n Off-board Outputs: Disabled\n\n", CMswitch);
break;
}
#ifdef WLAN_4RF_EN
//Turn on clocks to FMC
clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC | CLK_RFREF_OUTSEL_FMC));
//FMC samp clock divider = 2 (40MHz sampling reference, same as on-board AD9963 ref clk)
clk_config_dividers(CLK_BASEADDR, 2, CLK_SAMP_OUTSEL_FMC);
//FMC RF ref clock divider = 2 (40MHz RF reference, same as on-board MAX2829 ref clk)
clk_config_dividers(CLK_BASEADDR, 2, CLK_RFREF_OUTSEL_FMC);
#endif
//Initialize the AD9963 ADCs/DACs for on-board RF interfaces
ad_init(AD_BASEADDR, AD_ALL_RF, 3);
xil_printf("AD Readback: 0x%08x\n", ad_spi_read(AD_BASEADDR, RFA_AD_CS, 0x32));
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in ad_init (%d)\n", status);
ret = XST_FAILURE;
}
//Initialize the radio_controller core and MAX2829 transceivers for on-board RF interfaces
status = radio_controller_init(RC_BASEADDR, RC_ALL_RF, 1, 1);
if(status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in radioController_initialize (%d)\n", status);
//Comment out allow boot even if an RF interfce doesn't lock (hack for debugging - not for reference release)
ret = XST_FAILURE;
}
//Initialize the EEPROM read/write core
iic_eeprom_init(EEPROM_BASEADDR, 0x64);
#ifdef WLAN_4RF_EN
iic_eeprom_init(FMC_EEPROM_BASEADDR, 0x64);
#endif
//Initialize the timer counter
status = XTmrCtr_Initialize(TmrCtrInstancePtr, TMRCTR_DEVICE_ID);
if (status != XST_SUCCESS) {
xil_printf("w3_node_init: Error in XtmrCtr_Initialize (%d)\n", status);
ret = XST_FAILURE;
}
// Set timer 0 to into a "count down" mode
XTmrCtr_SetOptions(TmrCtrInstancePtr, 0, (XTC_DOWN_COUNT_OPTION));
//Give the PHY control of the red user LEDs (PHY counts 1-hot on SIGNAL errors)
//Note: Uncommenting this line will make the RED LEDs controlled by hardware.
//This will move the LEDs on PHY bad signal events
//userio_set_ctrlSrc_hw(USERIO_BASEADDR, W3_USERIO_CTRLSRC_LEDS_RED);
return ret;
}
