static void yx240qv29_enable(struct drm_simple_display_pipe *pipe,
struct drm_crtc_state *crtc_state,
struct drm_plane_state *plane_state)
{
struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
u8 addr_mode;
int ret, idx;
if (!drm_dev_enter(pipe->crtc.dev, &idx))
return;
DRM_DEBUG_KMS("\n");
ret = mipi_dbi_poweron_conditional_reset(mipi);
if (ret < 0)
goto out_exit;
if (ret == 1)
goto out_enable;
/* setextc */
mipi_dbi_command(mipi, HX8357D_SETEXTC, 0xFF, 0x83, 0x57);
msleep(150);
/* setRGB which also enables SDO */
mipi_dbi_command(mipi, HX8357D_SETRGB, 0x00, 0x00, 0x06, 0x06);
/* -1.52V */
mipi_dbi_command(mipi, HX8357D_SETCOM, 0x25);
/* Normal mode 70Hz, Idle mode 55 Hz */
mipi_dbi_command(mipi, HX8357D_SETOSC, 0x68);
/* Set Panel - BGR, Gate direction swapped */
mipi_dbi_command(mipi, HX8357D_SETPANEL, 0x05);
mipi_dbi_command(mipi, HX8357D_SETPOWER,
0x00, /* Not deep standby */
0x15, /* BT */
0x1C, /* VSPR */
0x1C, /* VSNR */
0x83, /* AP */
0xAA); /* FS */
mipi_dbi_command(mipi, HX8357D_SETSTBA,
0x50, /* OPON normal */
0x50, /* OPON idle */
0x01, /* STBA */
0x3C, /* STBA */
0x1E, /* STBA */
0x08); /* GEN */
mipi_dbi_command(mipi, HX8357D_SETCYC,
0x02, /* NW 0x02 */
0x40, /* RTN */
0x00, /* DIV */
0x2A, /* DUM */
0x2A, /* DUM */
0x0D, /* GDON */
0x78); /* GDOFF */
mipi_dbi_command(mipi, HX8357D_SETGAMMA,
0x02,
0x0A,
0x11,
0x1d,
0x23,
0x35,
0x41,
0x4b,
0x4b,
0x42,
0x3A,
0x27,
0x1B,
0x08,
0x09,
0x03,
0x02,
0x0A,
0x11,
0x1d,
0x23,
0x35,
0x41,
0x4b,
0x4b,
0x42,
0x3A,
0x27,
0x1B,
0x08,
0x09,
0x03,
0x00,
0x01);
/* 16 bit */
mipi_dbi_command(mipi, MIPI_DCS_SET_PIXEL_FORMAT,
MIPI_DCS_PIXEL_FMT_16BIT);
/* TE off */
mipi_dbi_command(mipi, MIPI_DCS_SET_TEAR_ON, 0x00);
/* tear line */
mipi_dbi_command(mipi, MIPI_DCS_SET_TEAR_SCANLINE, 0x00, 0x02);
/* Exit Sleep */
mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
msleep(150);
/* display on */
mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
usleep_range(5000, 7000);
out_enable:
switch (mipi->rotation) {
default:
addr_mode = HX8357D_MADCTL_MX | HX8357D_MADCTL_MY;
break;
case 90:
addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MY;
break;
case 180:
addr_mode = 0;
break;
case 270:
addr_mode = HX8357D_MADCTL_MV | HX8357D_MADCTL_MX;
break;
}
mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_enable_flush(mipi, crtc_state, plane_state);
out_exit:
drm_dev_exit(idx);
}
static void jd_t18003_t01_pipe_enable(struct drm_simple_display_pipe *pipe,
struct drm_crtc_state *crtc_state,
struct drm_plane_state *plane_state)
{
struct tinydrm_device *tdev = pipe_to_tinydrm(pipe);
struct mipi_dbi *mipi = mipi_dbi_from_tinydrm(tdev);
int ret;
u8 addr_mode;
DRM_DEBUG_KMS("\n");
ret = mipi_dbi_poweron_reset(mipi);
if (ret)
return;
msleep(150);
mipi_dbi_command(mipi, MIPI_DCS_EXIT_SLEEP_MODE);
msleep(500);
mipi_dbi_command(mipi, ST7735R_FRMCTR1, 0x01, 0x2c, 0x2d);
mipi_dbi_command(mipi, ST7735R_FRMCTR2, 0x01, 0x2c, 0x2d);
mipi_dbi_command(mipi, ST7735R_FRMCTR3, 0x01, 0x2c, 0x2d, 0x01, 0x2c,
0x2d);
mipi_dbi_command(mipi, ST7735R_INVCTR, 0x07);
mipi_dbi_command(mipi, ST7735R_PWCTR1, 0xa2, 0x02, 0x84);
mipi_dbi_command(mipi, ST7735R_PWCTR2, 0xc5);
mipi_dbi_command(mipi, ST7735R_PWCTR3, 0x0a, 0x00);
mipi_dbi_command(mipi, ST7735R_PWCTR4, 0x8a, 0x2a);
mipi_dbi_command(mipi, ST7735R_PWCTR5, 0x8a, 0xee);
mipi_dbi_command(mipi, ST7735R_VMCTR1, 0x0e);
mipi_dbi_command(mipi, MIPI_DCS_EXIT_INVERT_MODE);
switch (mipi->rotation) {
default:
addr_mode = ST7735R_MX | ST7735R_MY;
break;
case 90:
addr_mode = ST7735R_MX | ST7735R_MV;
break;
case 180:
addr_mode = 0;
break;
case 270:
addr_mode = ST7735R_MY | ST7735R_MV;
break;
}
mipi_dbi_command(mipi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
mipi_dbi_command(mipi, MIPI_DCS_SET_PIXEL_FORMAT,
MIPI_DCS_PIXEL_FMT_16BIT);
mipi_dbi_command(mipi, ST7735R_GAMCTRP1, 0x02, 0x1c, 0x07, 0x12, 0x37,
0x32, 0x29, 0x2d, 0x29, 0x25, 0x2b, 0x39, 0x00, 0x01,
0x03, 0x10);
mipi_dbi_command(mipi, ST7735R_GAMCTRN1, 0x03, 0x1d, 0x07, 0x06, 0x2e,
0x2c, 0x29, 0x2d, 0x2e, 0x2e, 0x37, 0x3f, 0x00, 0x00,
0x02, 0x10);
mipi_dbi_command(mipi, MIPI_DCS_SET_DISPLAY_ON);
msleep(100);
mipi_dbi_command(mipi, MIPI_DCS_ENTER_NORMAL_MODE);
msleep(20);
mipi_dbi_enable_flush(mipi, crtc_state, plane_state);
}
