C++ (Cpp) mipi_dsi_configure_serdes Examples

Example #1

void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
	int target_type)
{
	struct mipi_dsi_phy_ctrl *pd;
	int i, off;

	MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
#ifdef CONFIG_MACH_ACER_A9
	usleep_range(2000, 2000);
#else
	msleep(100);
#endif
	MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
	MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */

	pd = (panel_info->mipi).dsi_phy_db;

	off = 0x0480;	/* strength 0 - 2 */
	for (i = 0; i < 3; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
		wmb();
		off += 4;
	}

	off = 0x0470;	/* ctrl 0 - 3 */
	for (i = 0; i < 4; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
		wmb();
		off += 4;
	}

	off = 0x0500;	/* regulator ctrl 0 - 4 */
	for (i = 0; i < 5; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
		wmb();
		off += 4;
	}
	mipi_dsi_calibration();

	off = 0x0204;	/* pll ctrl 1 - 19, skip 0 */
	for (i = 1; i < 20; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
		wmb();
		off += 4;
	}

	if (panel_info)
		mipi_dsi_phy_pll_config(panel_info->clk_rate);

	/* pll ctrl 0 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
	wmb();

	off = 0x0440;	/* phy timing ctrl 0 - 11 */
	for (i = 0; i < 12; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
		wmb();
		off += 4;
	}

	if (target_type == 1)
		mipi_dsi_configure_serdes();
}

Example #2

void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
                       int target_type)
{
    struct mipi_dsi_phy_ctrl *pd;
    int i, off;

    MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
    wmb();
    usleep(1);
    MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
    wmb();
    usleep(1);
    MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */
    MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */
    MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */
    MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */
    MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */

    MIPI_OUTP(MIPI_DSI_BASE + 0x4b0, 0x04);/* DSIPHY_LDO_CNTRL */

    pd = (panel_info->mipi).dsi_phy_db;

    off = 0x0480;	/* strength 0 - 2 */
    for (i = 0; i < 3; i++) {
        MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
        wmb();
        off += 4;
    }

    off = 0x0470;	/* ctrl 0 - 3 */
    for (i = 0; i < 4; i++) {
        MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
        wmb();
        off += 4;
    }

    off = 0x0500;	/* regulator ctrl 0 - 4 */
    for (i = 0; i < 5; i++) {
        MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
        wmb();
        off += 4;
    }
    mipi_dsi_calibration();
    mipi_dsi_lane_cfg(); /* lane cfgs */
    mipi_dsi_bist_ctrl(); /* bist ctrl */

    off = 0x0204;	/* pll ctrl 1 - 19, skip 0 */
    for (i = 1; i < 20; i++) {
        MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
        wmb();
        off += 4;
    }

    if (!panel_info)
        pr_err("%s: panel_info not initialized\n", __func__);
    else
        mipi_dsi_phy_pll_config(panel_info->clk_rate);

    /* pll ctrl 0 */
    MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
    wmb();

    off = 0x0440;	/* phy timing ctrl 0 - 11 */
    for (i = 0; i < 12; i++) {
        MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
        wmb();
        off += 4;
    }

    if (target_type == 1)
        mipi_dsi_configure_serdes();
}

Example #3

void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
	int target_type)
{
	struct mipi_dsi_phy_ctrl *pd;
	int i, off;

	MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
	wmb();
#ifdef CONFIG_SHLCDC_BOARD /* CUST_ID_00049 */ /* CUST_ID_00082 */
	mipi_sharp_delay_us(1);
#else	/* CONFIG_SHLCDC_BOARD */
	usleep(1);
#endif	/* CONFIG_SHLCDC_BOARD */
	MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
	wmb();
#ifdef CONFIG_SHLCDC_BOARD /* CUST_ID_00049 */ /* CUST_ID_00082 */
	mipi_sharp_delay_us(1);
#else	/* CONFIG_SHLCDC_BOARD */
	usleep(1);
#endif	/* CONFIG_SHLCDC_BOARD */
	MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */

	MIPI_OUTP(MIPI_DSI_BASE + 0x4b0, 0x04);/* DSIPHY_LDO_CNTRL */

	pd = (panel_info->mipi).dsi_phy_db;

	off = 0x0480;	/* strength 0 - 2 */
	for (i = 0; i < 3; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
		wmb();
		off += 4;
	}

	off = 0x0470;	/* ctrl 0 - 3 */
	for (i = 0; i < 4; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
		wmb();
		off += 4;
	}

	off = 0x0500;	/* regulator ctrl 0 - 4 */
	for (i = 0; i < 5; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
		wmb();
		off += 4;
	}
	mipi_dsi_calibration();
	mipi_dsi_lane_cfg(); /* lane cfgs */
	mipi_dsi_bist_ctrl(); /* bist ctrl */

	off = 0x0204;	/* pll ctrl 1 - 19, skip 0 */
	for (i = 1; i < 20; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
		wmb();
		off += 4;
	}

#ifndef CONFIG_SHLCDC_BOARD /* CUST_ID_00005 */
	if (panel_info)
		mipi_dsi_phy_pll_config(panel_info->clk_rate);
#endif /* CONFIG_SHLCDC_BOARD */

	/* pll ctrl 0 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
	wmb();

	off = 0x0440;	/* phy timing ctrl 0 - 11 */
	for (i = 0; i < 12; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
		wmb();
		off += 4;
	}

	if (target_type == 1)
		mipi_dsi_configure_serdes();
}

Example #4

File: msm_dss_io_8960.c Project: Ca1ne/Enoch316

void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
	int target_type)
{
	struct mipi_dsi_phy_ctrl *pd;
	int i, off;

	MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);
	wmb();
	usleep(1);
	MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);
	wmb();
	usleep(1);
	MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);
	MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);
	MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);
	MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);
	MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);

	MIPI_OUTP(MIPI_DSI_BASE + 0x4b0, 0x04);

	pd = (panel_info->mipi).dsi_phy_db;

	off = 0x0480;	
	for (i = 0; i < 3; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
		wmb();
		off += 4;
	}

	off = 0x0470;	
	for (i = 0; i < 4; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
		wmb();
		off += 4;
	}

	off = 0x0500;	
	for (i = 0; i < 5; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
		wmb();
		off += 4;
	}
	mipi_dsi_calibration();
	mipi_dsi_lane_cfg(); 
	mipi_dsi_bist_ctrl(); 

	off = 0x0204;	
	for (i = 1; i < 20; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
		wmb();
		off += 4;
	}

	if (panel_info)
		mipi_dsi_phy_pll_config(panel_info->clk_rate);

	
	MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
	wmb();

	off = 0x0440;	
	for (i = 0; i < 12; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
		wmb();
		off += 4;
	}

	if (target_type == 1)
		mipi_dsi_configure_serdes();
}

Example #5

File: msm_dss_io_8960.c Project: manl/pubile

void mipi_dsi_phy_init(int panel_ndx, struct msm_panel_info const *panel_info,
	int target_type)
{
	struct mipi_dsi_phy_ctrl *pd = NULL;
	int i, off;

	MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0001);/* start phy sw reset */
	wmb();
	usleep(1);
	MIPI_OUTP(MIPI_DSI_BASE + 0x128, 0x0000);/* end phy w reset */
	wmb();
	usleep(1);
	MIPI_OUTP(MIPI_DSI_BASE + 0x500, 0x0003);/* regulator_ctrl_0 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x504, 0x0001);/* regulator_ctrl_1 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x508, 0x0001);/* regulator_ctrl_2 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x50c, 0x0000);/* regulator_ctrl_3 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x510, 0x0100);/* regulator_ctrl_4 */

	MIPI_OUTP(MIPI_DSI_BASE + 0x4b0, 0x04);/* DSIPHY_LDO_CNTRL */

	//rms
	for (i = 0; i < (panel_info->mipi).dsi_phy_db_count; i++) {
		pd = (panel_info->mipi).dsi_phy_db[i];
		if ((panel_info->mipi).frame_rate == pd->frame) {
			printk(KERN_ERR"(%s:%d) use frame_rate %d %d",
			       __FUNCTION__, __LINE__,
			       i, pd->frame);
			break;
		}
	}
	if (i >= (panel_info->mipi).dsi_phy_db_count) {
		pd = (panel_info->mipi).dsi_phy_db[0];
		printk(KERN_ERR"(%s:%d) cannot support %d %d %d, use default",
		       __FUNCTION__, __LINE__,
		       (panel_info->mipi).frame_rate, i, pd->frame);
	}
	//end
	

	off = 0x0480;	/* strength 0 - 2 */
	for (i = 0; i < 3; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->strength[i]);
		wmb();
		off += 4;
	}

	off = 0x0470;	/* ctrl 0 - 3 */
	for (i = 0; i < 4; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->ctrl[i]);
		wmb();
		off += 4;
	}

	off = 0x0500;	/* regulator ctrl 0 - 4 */
	for (i = 0; i < 5; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->regulator[i]);
		wmb();
		off += 4;
	}
	mipi_dsi_calibration();
	mipi_dsi_lane_cfg(); /* lane cfgs */
	mipi_dsi_bist_ctrl(); /* bist ctrl */

	off = 0x0204;	/* pll ctrl 1 - 19, skip 0 */
	for (i = 1; i < 20; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->pll[i]);
		wmb();
		off += 4;
	}

	if (panel_info) {
		printk(KERN_ERR"rms:(%s:%d) clk_rate %u", __FUNCTION__, __LINE__, panel_info->clk_rate);
		mipi_dsi_phy_pll_config(panel_info->clk_rate);
	}

	/* pll ctrl 0 */
	MIPI_OUTP(MIPI_DSI_BASE + 0x200, pd->pll[0]);
	wmb();

	off = 0x0440;	/* phy timing ctrl 0 - 11 */
	for (i = 0; i < 12; i++) {
		MIPI_OUTP(MIPI_DSI_BASE + off, pd->timing[i]);
		wmb();
		off += 4;
	}

	if (target_type == 1)
		mipi_dsi_configure_serdes();
}