void extcl_cpu_wr_mem_217(WORD address, BYTE value) {
if (address > 0x7FFF) {
switch (address & 0xE001) {
case 0x8000:
if (!m217.reg[2]) {
m217_8000()
} else {
extcl_cpu_wr_mem_MMC3(0xC000, value);
}
return;
case 0x8001: {
if (!m217.reg[2]) {
m217_8001()
} else {
static const BYTE security[8] = { 0, 6, 3, 7, 5, 2, 4, 1};
BYTE save = value;
m217.reg[3] = TRUE;
value = (save & 0xC0) | security[save & 0x07];
m217_8000()
}
return;
}
case 0xA000:
if (!m217.reg[2]) {
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
} else {
if (m217.reg[3] && (!(m217.reg[0] & 0x80) || (mmc3.bank_to_update < 6))) {
m217.reg[3] = FALSE;
m217_8001()
}
}
return;
case 0xA001:
if (!m217.reg[2]) {
extcl_cpu_wr_mem_MMC3(address, value);
} else {
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
}
return;
}
extcl_cpu_wr_mem_MMC3(address, value);
return;
}
void extcl_cpu_wr_mem_Irem_G101(WORD address, BYTE value) {
if (address >= 0xC000) {
return;
}
switch (address & 0xF000) {
case 0x8000:
irem_G101.prg_reg = value;
irem_G101_prg_rom_update();
break;
case 0x9000:
if (info.mapper.submapper != G101B) {
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
}
irem_G101.prg_mode = value & 0x02;
value = irem_G101.prg_reg;
irem_G101_prg_rom_update();
break;
case 0xA000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
map_prg_rom_8k_update();
break;
case 0xB000:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[address & 0x0007] = chr_chip_byte_pnt(0, value << 10);
break;
}
}
void extcl_cpu_wr_mem_200(WORD address, BYTE value) {
BYTE save = (address & 0xFF);
DBWORD bank;
value = save;
control_bank(info.prg.rom.max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k(2, 2, value);
map_prg_rom_8k_update();
value = save;
control_bank(info.chr.rom.max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
if (address & 0x0008) {
mirroring_H();
} else {
mirroring_V();
}
}
void extcl_cpu_wr_mem_233(WORD address, BYTE value) {
BYTE save = value;
value &= 0x1F;
if (save & 0x20) {
control_bank(info.prg.rom.max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k(2, 2, value);
} else {
value >>= 1;
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
}
map_prg_rom_8k_update();
switch ((save & 0xC0) >> 6) {
case 0:
mirroring_SCR0x3_SCR1x1();
break;
case 1:
mirroring_V();
break;
case 2:
mirroring_H();
break;
case 3:
mirroring_SCR1();
break;
}
}
void extcl_cpu_wr_mem_BMC70IN1(WORD address, BYTE value) {
if (address & 0x4000) {
bmc70in1.reg[0] = address & 0x30;
bmc70in1.reg[1] = address & 0x07;
} else {
if (address & 0x20) {
mirroring_H();
} else {
mirroring_V();
}
if (bmc70in1_type == BMC70IN1B) {
bmc70in1.reg[2] = (address & 0x03) << 3;
} else {
DBWORD bank;
value = address & 0x07;
control_bank(info.chr.rom[0].max.banks_8k)
bank = value << 13;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank | 0x0800);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0C00);
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank | 0x1000);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x1400);
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank | 0x1800);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x1C00);
}
}
switch (bmc70in1.reg[0]) {
case 0x00:
case 0x10:
value = bmc70in1.reg[2] | bmc70in1.reg[1];
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 0, value);
value = bmc70in1.reg[2] | 0x07;
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 2, value);
break;
case 0x20:
value = (bmc70in1.reg[2] | bmc70in1.reg[1]) >> 1;
control_bank(info.prg.rom[0].max.banks_32k)
map_prg_rom_8k(4, 0, value);
break;
case 0x30:
value = bmc70in1.reg[2] | bmc70in1.reg[1];
control_bank(info.prg.rom[0].max.banks_16k)
map_prg_rom_8k(2, 0, value);
map_prg_rom_8k(2, 2, value);
break;
}
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_242(WORD address, BYTE value) {
if (address & 0x0002) {
mirroring_H();
} else {
mirroring_V();
}
value = (address & 0x0078) >> 3;
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_Hen_177(WORD address, BYTE value) {
if (type != HEN_FANKONG) {
if (value & 0x20) {
mirroring_H();
} else {
mirroring_V();
}
}
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
map_prg_rom_8k_update();
}
void extcl_cpu_wr_mem_Ntdec_asder(WORD address, BYTE value) {
switch (address & 0xE001) {
case 0x8000:
asder.address = value & 0x07;
return;
case 0xA000: {
switch (asder.address) {
case 0:
case 1:
control_bank(info.prg.rom.max.banks_8k)
map_prg_rom_8k(1, asder.address, value);
map_prg_rom_8k_update();
return;
case 2:
case 3:
asder.reg[asder.address] = value >> 1;
break;
case 4:
case 5:
case 6:
case 7:
asder.reg[asder.address] = value;
break;
}
break;
}
case 0xC000:
asder.reg[0] = value;
break;
case 0xE000:
asder.reg[1] = value;
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
break;
}
{
DBWORD bank;
const WORD chr_high = (asder.reg[1] & 0x02) ? asder.reg[0] : 0;
WORD new_value;
asder_chr_2k_update(5, 2, 0, 1);
asder_chr_2k_update(4, 3, 2, 3);
asder_chr_1k_update(4, 4);
asder_chr_1k_update(3, 5);
asder_chr_1k_update(2, 6);
asder_chr_1k_update(1, 7);
}
}
void extcl_cpu_wr_mem_Irem_H3000(WORD address, BYTE value) {
switch (address & 0xF000) {
case 0x8000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 0, value);
map_prg_rom_8k_update();
break;
case 0x9000: {
switch (address & 0x0007) {
case 1:
if (value & 0x80) {
mirroring_H();
} else {
mirroring_V();
}
break;
case 3:
irem_H3000.enable = value & 0x80;
irq.high &= ~EXT_IRQ;
break;
case 4:
irem_H3000.count = irem_H3000.reload;
irq.high &= ~EXT_IRQ;
break;
case 5:
irem_H3000.reload = (irem_H3000.reload & 0x00FF) | (value << 8);
break;
case 6:
irem_H3000.reload = (irem_H3000.reload & 0xFF00) | value;
break;
}
break;
}
case 0xB000:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[address & 0x0007] = chr_chip_byte_pnt(0, value << 10);
break;
case 0xA000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 1, value);
map_prg_rom_8k_update();
break;
case 0xC000:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, 2, value);
map_prg_rom_8k_update();
break;
}
}
void extcl_cpu_wr_mem_57(WORD address, BYTE value) {
DBWORD bank;
if (address & 0x0800) {
m57.reg[0] = value;
if (m57.reg[0] & 0x08) {
mirroring_H();
} else {
mirroring_V();
}
if (m57.reg[0] & 0x10) {
value = (m57.reg[0] & 0xC0) >> 6;
control_bank(info.prg.rom.max.banks_32k)
map_prg_rom_8k(4, 0, value);
} else {
void extcl_cpu_wr_mem_SC_127(WORD address, BYTE value) {
switch (address) {
case 0x8000:
case 0x8001:
case 0x8002:
control_bank(info.prg.rom[0].max.banks_8k)
map_prg_rom_8k(1, address & 0x03, value);
map_prg_rom_8k_update();
return;
case 0x9000:
case 0x9001:
case 0x9002:
case 0x9003:
case 0x9004:
case 0x9005:
case 0x9006:
case 0x9007:
control_bank(info.chr.rom[0].max.banks_1k)
chr.bank_1k[address & 0x07] = chr_chip_byte_pnt(0, value << 10);
return;
case 0xC002:
sc127.irq.active = 0;
irq.high &= ~EXT_IRQ;
return;
case 0xC003:
sc127.irq.active = 1;
return;
case 0xC005:
sc127.irq.count = value;
return;
case 0xD001:
if (value & 0x01) {
mirroring_H();
} else {
mirroring_V();
}
return;
}
}
static void INLINE sync_83(void) {
WORD value;
switch (m83.mode & 0x03) {
case 0:
mirroring_V();
break;
case 1:
mirroring_H();
break;
case 2:
mirroring_SCR0();
break;
case 3:
mirroring_SCR1();
break;
}
if (m83.is2kbank && !m83.isnot2kbank) {
SDBWORD bank;
value = m83.reg[0];
control_bank(info.chr.rom.max.banks_2k)
bank = value << 11;
chr.bank_1k[0] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[1] = chr_chip_byte_pnt(0, bank | 0x0400);
value = m83.reg[1];
control_bank(info.chr.rom.max.banks_2k)
bank = value << 11;
chr.bank_1k[2] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[3] = chr_chip_byte_pnt(0, bank | 0x0400);
value = m83.reg[6];
control_bank(info.chr.rom.max.banks_2k)
bank = value << 11;
chr.bank_1k[4] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[5] = chr_chip_byte_pnt(0, bank | 0x0400);
value = m83.reg[7];
control_bank(info.chr.rom.max.banks_2k)
bank = value << 11;
chr.bank_1k[6] = chr_chip_byte_pnt(0, bank);
chr.bank_1k[7] = chr_chip_byte_pnt(0, bank | 0x0400);
} else {
BYTE i;
for (i = 0; i < 8; i++) {
value = ((m83.bank << 4) & 0x0300) | m83.reg[i];
control_bank(info.chr.rom.max.banks_1k)
chr.bank_1k[i] = chr_chip_byte_pnt(0, value << 10);
}
}
if (m83.mode & 0x40) {
value = (m83.bank & 0x3F);
control_bank(info.prg.rom.max.banks_16k)
map_prg_rom_8k(2, 0, value);
value = (m83.bank & 0x30) | 0x0F;
control_bank(info.prg.rom.max.banks_16k)
map_prg_rom_8k(2, 2, value);
} else {
value = m83.reg[8];
control_bank(info.prg.rom.max.banks_8k)
map_prg_rom_8k(1, 0, value);
value = m83.reg[9];
control_bank(info.prg.rom.max.banks_8k)
map_prg_rom_8k(1, 1, value);
value = m83.reg[10];
control_bank(info.prg.rom.max.banks_8k)
map_prg_rom_8k(1, 2, value);
map_prg_rom_8k(1, 3, info.prg.rom.max.banks_8k);
}
map_prg_rom_8k_update();
}
