Example #1
0
/**
 * mn10300_dcache_flush_inv - Globally flush and invalidate data cache
 *
 * Flush and invalidate the data cache on all CPUs.
 */
void mn10300_dcache_flush_inv(void)
{
	unsigned long flags;

	flags = smp_lock_cache();
	mn10300_local_dcache_flush_inv();
	smp_cache_call(SMP_DCACHE_FLUSH_INV, 0, 0);
	smp_unlock_cache(flags);
}
/**
 * smp_cache_interrupt - Handle IPI request to flush caches.
 *
 * Handle a request delivered by IPI to flush the current CPU's
 * caches.  The parameters are stored in smp_cache_*.
 */
void smp_cache_interrupt(void)
{
	unsigned long opr_mask = smp_cache_mask;

	switch ((enum smp_dcache_ops)(opr_mask & SMP_DCACHE_OP_MASK)) {
	case SMP_DCACHE_NOP:
		break;
	case SMP_DCACHE_INV:
		mn10300_local_dcache_inv();
		break;
	case SMP_DCACHE_INV_RANGE:
		mn10300_local_dcache_inv_range(smp_cache_start, smp_cache_end);
		break;
	case SMP_DCACHE_FLUSH:
		mn10300_local_dcache_flush();
		break;
	case SMP_DCACHE_FLUSH_RANGE:
		mn10300_local_dcache_flush_range(smp_cache_start,
						 smp_cache_end);
		break;
	case SMP_DCACHE_FLUSH_INV:
		mn10300_local_dcache_flush_inv();
		break;
	case SMP_DCACHE_FLUSH_INV_RANGE:
		mn10300_local_dcache_flush_inv_range(smp_cache_start,
						     smp_cache_end);
		break;
	}

	switch ((enum smp_icache_ops)(opr_mask & SMP_ICACHE_OP_MASK)) {
	case SMP_ICACHE_NOP:
		break;
	case SMP_ICACHE_INV:
		mn10300_local_icache_inv();
		break;
	case SMP_ICACHE_INV_RANGE:
		mn10300_local_icache_inv_range(smp_cache_start, smp_cache_end);
		break;
	}

	cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map);
}