static void mpulcd_display_on(void) { mpulcd_setup_pannel_register(CMD, 0x29); lcdif_write(HW_LCDIF_CTRL1_SET, BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN); mpulcd_start_refresh(); }
static irqreturn_t lcd_irq_handler(int irq, void *dev_id) { struct mxs_fb_data *data = dev_id; u32 status_lcd = __raw_readl(data->regbase + HW_LCDIF_CTRL1); pr_debug("%s: irq %d\n", __func__, irq); if (status_lcd & BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ) { pr_debug("%s: VSYNC irq\n", __func__); data->vsync_count++; __raw_writel(BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ, data->regbase + HW_LCDIF_CTRL1_CLR); wake_up_interruptible(&data->vsync_wait_q); } if (status_lcd & BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ) { pr_debug("%s: frame done irq\n", __func__); //SSD1963 mpulcd_start_refresh(); __raw_writel(BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ, data->regbase + HW_LCDIF_CTRL1_CLR); //SSD1963 //data->vsync_count++; } if (status_lcd & BM_LCDIF_CTRL1_UNDERFLOW_IRQ) { pr_debug("%s: underflow irq\n", __func__); __raw_writel(BM_LCDIF_CTRL1_UNDERFLOW_IRQ, data->regbase + HW_LCDIF_CTRL1_CLR); } if (status_lcd & BM_LCDIF_CTRL1_OVERFLOW_IRQ) { pr_debug("%s: overflow irq\n", __func__); __raw_writel(BM_LCDIF_CTRL1_OVERFLOW_IRQ, data->regbase + HW_LCDIF_CTRL1_CLR); } return IRQ_HANDLED; }