static irqreturn_t msm_csiphy_irq(int irq_num, void *data)
{
uint32_t irq;
struct csiphy_device *csiphy_dev = data;
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS0_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS0 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS1_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR1_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS1 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS2_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR2_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS2 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS3_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR3_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS3 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS4_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR4_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS4 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
msm_io_w(0x1, csiphy_dev->base + 0x164);
msm_io_w(0x0, csiphy_dev->base + 0x164);
return IRQ_HANDLED;
}
void msm_send_frame_to_vpe(uint32_t pyaddr, uint32_t pcbcraddr,
struct timespec *ts)
{
uint32_t temp_pyaddr, temp_pcbcraddr;
CDBG("vpe input, pyaddr = 0x%x, pcbcraddr = 0x%x\n",
pyaddr, pcbcraddr);
msm_io_w(pyaddr, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w(pcbcraddr, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == 1)
CDBG(" =====VPE is busy!!! Wrong!========\n");
else
vpe_ctrl->ts = *ts;
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
vpe_ctrl->state = 1;
vpe_start();
}
static void msm_ispif_enable_intf_cids(uint8_t intftype, uint16_t cid_mask)
{
uint32_t data;
mutex_lock(&ispif->mutex);
switch (intftype) {
case PIX0:
data = msm_io_r(ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
data |= cid_mask;
msm_io_w(data, ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
break;
case RDI0:
data = msm_io_r(ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
data |= cid_mask;
msm_io_w(data, ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
break;
case RDI1:
data = msm_io_r(ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
data |= cid_mask;
msm_io_w(data, ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
break;
}
mutex_unlock(&ispif->mutex);
}
static int msm_ispif_config(struct msm_ispif_params_list *params_list)
{
uint32_t params_len;
struct msm_ispif_params *ispif_params;
uint32_t data, data1;
int rc = 0, i = 0;
params_len = params_list->len;
ispif_params = params_list->params;
CDBG("Enable interface\n");
data = msm_io_r(ispif->base + ISPIF_PIX_STATUS_ADDR);
data1 = msm_io_r(ispif->base + ISPIF_RDI_STATUS_ADDR);
if (((data & 0xf) != 0xf) || ((data1 & 0xf) != 0xf))
return -EBUSY;
msm_io_w(0x00000000, ispif->base + ISPIF_IRQ_MASK_ADDR);
for (i = 0; i < params_len; i++) {
msm_ispif_sel_csid_core(ispif_params[i].intftype,
ispif_params[i].csid);
msm_ispif_enable_intf_cids(ispif_params[i].intftype,
ispif_params[i].cid_mask);
}
msm_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
ISPIF_IRQ_MASK_ADDR);
msm_io_w(ISPIF_IRQ_STATUS_MASK, ispif->base +
ISPIF_IRQ_CLEAR_ADDR);
msm_io_w(ISPIF_IRQ_GLOBAL_CLEAR_CMD, ispif->base +
ISPIF_IRQ_GLOBAL_CLEAR_CMD_ADDR);
return rc;
}
void msm_camio_csi_core_reset(void)
{
uint32_t val;
val = msm_io_r(MSM_MMSS_CLK_CTL_BASE + 0x210);
msm_io_w(val | 0x1000100, MSM_MMSS_CLK_CTL_BASE + 0x210);
#if 0
val = msm_io_r(clkctl + 0x20C);
msm_io_w(val | 0x20000, clkctl + 0x20C);
#endif
}
static void vpe_do_tasklet(unsigned long data)
{
unsigned long flags;
uint32_t pyaddr, pcbcraddr, src_y, src_cbcr, temp;
struct vpe_isr_queue_cmd_type *qcmd = NULL;
CDBG("=== vpe_do_tasklet start === \n");
spin_lock_irqsave(&vpe_ctrl->tasklet_lock, flags);
qcmd = list_first_entry(&vpe_ctrl->tasklet_q,
struct vpe_isr_queue_cmd_type, list);
if (!qcmd) {
spin_unlock_irqrestore(&vpe_ctrl->tasklet_lock, flags);
return;
}
list_del(&qcmd->list);
spin_unlock_irqrestore(&vpe_ctrl->tasklet_lock, flags);
/* interrupt to be processed, *qcmd has the payload. */
if (qcmd->irq_status & 0x1) {
CDBG("vpe plane0 frame done.\n");
pyaddr =
msm_io_r(vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
pcbcraddr =
msm_io_r(vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
if (vpe_ctrl->dis_en)
pcbcraddr = vpe_ctrl->pcbcr_before_dis;
src_y =
msm_io_r(vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
src_cbcr =
msm_io_r(vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
msm_io_w(src_y,
vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
msm_io_w(src_cbcr,
vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
temp = msm_io_r(
vpe_device->vpebase + VPE_OP_MODE_OFFSET) & 0xFFFFFFFC;
msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
CDBG("vpe send out msg.\n");
/* now pass this frame to msm_camera.c. */
vpe_send_outmsg(MSG_ID_VPE_OUTPUT_V, pyaddr, pcbcraddr);
vpe_ctrl->state = 0; /* put it back to idle. */
}
kfree(qcmd);
}
void msm_send_frame_to_vpe(uint32_t pyaddr, uint32_t pcbcraddr,
struct timespec *ts, int output_type)
{
uint32_t temp_pyaddr = 0, temp_pcbcraddr = 0;
CDBG("[CAM] vpe input, pyaddr = 0x%x, pcbcraddr = 0x%x\n",
pyaddr, pcbcraddr);
msm_io_w(pyaddr, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w(pcbcraddr, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == 1)
pr_err("[CAM] =====VPE is busy!!! Wrong!========\n");
if (output_type != OUTPUT_TYPE_ST_R)
vpe_ctrl->ts = *ts;
if (output_type == OUTPUT_TYPE_ST_L) {
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
if (vpe_ctrl->frame_pack == TOP_DOWN_FULL)
temp_pcbcraddr = temp_pyaddr + (vpe_ctrl->out_w * vpe_ctrl->out_h * 2);
else if ((vpe_ctrl->frame_pack == SIDE_BY_SIDE_HALF) ||
(vpe_ctrl->frame_pack == SIDE_BY_SIDE_FULL))
temp_pcbcraddr = temp_pyaddr +
PAD_TO_2K((vpe_ctrl->out_w * 2) * vpe_ctrl->out_h,
vpe_ctrl->pad_2k_bool);
else
CDBG("[CAM] %s: Invalid Frame Packing = %d\n", __func__,
vpe_ctrl->frame_pack);
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
vpe_ctrl->output_type = output_type;
vpe_ctrl->state = 1;
vpe_start();
}
static irqreturn_t msm_io_csi_irq(int irq_num, void *data)
{
uint32_t irq;
irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
save_mipi_irq = irq;
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
#if 0 //=> Add from
//bits 23:8 indicate word count
irq = msm_io_r(csibase + 0x00000010);
CDBG("%s MIPI_PROTOCOL_STATUS = 0x%x\n", __func__, irq);
#endif //=> Adde to
return IRQ_HANDLED;
}
void msm_camio_camif_pad_reg_reset_2(void)
{
uint32_t reg;
uint32_t mask, value;
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
msm_io_w((reg & (~mask)) | (value & mask), camifpadbase);
mdelay(10);
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
msm_io_w((reg & (~mask)) | (value & mask), camifpadbase);
mdelay(10);
}
static void msm_camio_csi_disable(void)
{
uint32_t val;
val = 0x0;
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(10);
val = msm_io_r(csibase + MIPI_PHY_D1_CONTROL);
val &= ~((0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT));
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
usleep_range(5000, 6000);
msm_io_w(0x0, csibase + MIPI_INTERRUPT_MASK);
msm_io_w(0x0, csibase + MIPI_INTERRUPT_STATUS);
csi_free_irq();
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
}
static int msm_csid_release(struct v4l2_subdev *sd)
{
uint32_t irq;
struct csid_device *csid_dev;
csid_dev = v4l2_get_subdevdata(sd);
irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
msm_io_w(0, csid_dev->base + CSID_IRQ_MASK_ADDR);
free_irq(csid_dev->irq->start, csid_dev);
msm_cam_clk_enable(&csid_dev->pdev->dev, csid_clk_info,
csid_dev->csid_clk, ARRAY_SIZE(csid_clk_info), 0);
msm_camera_enable_vreg(&csid_dev->pdev->dev, csid_vreg_info,
ARRAY_SIZE(csid_vreg_info), &csid_dev->csi_vdd, 0);
msm_camera_config_vreg(&csid_dev->pdev->dev, csid_vreg_info,
ARRAY_SIZE(csid_vreg_info), &csid_dev->csi_vdd, 0);
iounmap(csid_dev->base);
csid_dev->base = NULL;
return 0;
}
static irqreturn_t msm_csid_irq(int irq_num, void *data)
{
uint32_t irq;
struct csid_device *csid_dev = data;
irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
CDBG("%s CSID_IRQ_STATUS_ADDR = 0x%x\n", __func__, irq);
msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
if (irq & 0x100) {
printk(KERN_DEBUG "Long p.c.: %x, short : %x\n",
msm_io_r(csid_dev->base + 0x74),
msm_io_r(csid_dev->base + 0x70));
msm_io_w(0x19 , csid_dev->base + 0x08);
}
return IRQ_HANDLED;
}
void msm_camio_mode_config(enum msm_cam_mode mode)
{
uint32_t val;
val = msm_io_r(s3d_ctl);
if (mode == MODE_DUAL) {
msm_io_w(val | 0x3, s3d_ctl);
} else if (mode == MODE_L) {
msm_io_w(((val | 0x2) & ~(0x1)), s3d_ctl);
val = msm_io_r(s3d_ctl);
CDBG("the camio mode config left value is %d\n", val);
} else {
msm_io_w(((val | 0x1) & ~(0x2)), s3d_ctl);
val = msm_io_r(s3d_ctl);
CDBG("the camio mode config right value is %d\n", val);
}
}
static int vpe_reset(void)
{
uint32_t vpe_version;
uint32_t rc = 0;
/* */
unsigned long flags = 0;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
if (vpe_ctrl->state == VPE_STATE_IDLE) {
CDBG("%s: VPE already disabled.", __func__);
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
return rc;
}
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
/* */
vpe_reset_state_variables();
vpe_version = msm_io_r(vpe_ctrl->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
/* disable all interrupts.*/
msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
/* clear all pending interrupts*/
msm_io_w(0x1fffff, vpe_ctrl->vpebase + VPE_INTR_CLEAR_OFFSET);
/* write sw_reset to reset the core. */
msm_io_w(0x10, vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET);
/* then poll the reset bit, it should be self-cleared. */
while (1) {
rc =
msm_io_r(vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
if (rc == 0)
break;
}
/* at this point, hardware is reset. Then pogram to default
values. */
msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_ctrl->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
msm_io_w(VPE_CGC_ENABLE_VALUE,
vpe_ctrl->vpebase + VPE_CGC_EN_OFFSET);
msm_io_w(1, vpe_ctrl->vpebase + VPE_CMD_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_ctrl->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
return rc;
}
static int msm_csid_init(struct v4l2_subdev *sd, uint32_t *csid_version)
{
int rc = 0;
struct csid_device *csid_dev;
csid_dev = v4l2_get_subdevdata(sd);
if (csid_dev == NULL) {
rc = -ENOMEM;
return rc;
}
csid_dev->base = ioremap(csid_dev->mem->start,
resource_size(csid_dev->mem));
if (!csid_dev->base) {
rc = -ENOMEM;
return rc;
}
rc = msm_camera_config_vreg(&csid_dev->pdev->dev, csid_vreg_info,
ARRAY_SIZE(csid_vreg_info), &csid_dev->csi_vdd, 1);
if (rc < 0) {
pr_err("%s: regulator on failed\n", __func__);
goto vreg_config_failed;
}
rc = msm_camera_enable_vreg(&csid_dev->pdev->dev, csid_vreg_info,
ARRAY_SIZE(csid_vreg_info), &csid_dev->csi_vdd, 1);
if (rc < 0) {
pr_err("%s: regulator enable failed\n", __func__);
goto vreg_enable_failed;
}
rc = msm_cam_clk_enable(&csid_dev->pdev->dev, csid_clk_info,
csid_dev->csid_clk, ARRAY_SIZE(csid_clk_info), 1);
if (rc < 0) {
pr_err("%s: regulator enable failed\n", __func__);
goto clk_enable_failed;
}
csid_dev->hw_version =
msm_io_r(csid_dev->base + CSID_HW_VERSION_ADDR);
*csid_version = csid_dev->hw_version;
#if DBG_CSID
enable_irq(csid_dev->irq->start);
#endif
return 0;
clk_enable_failed:
msm_camera_enable_vreg(&csid_dev->pdev->dev, csid_vreg_info,
ARRAY_SIZE(csid_vreg_info), &csid_dev->csi_vdd, 0);
vreg_enable_failed:
msm_camera_config_vreg(&csid_dev->pdev->dev, csid_vreg_info,
ARRAY_SIZE(csid_vreg_info), &csid_dev->csi_vdd, 0);
vreg_config_failed:
iounmap(csid_dev->base);
csid_dev->base = NULL;
return rc;
}
static irqreturn_t msm_io_csi_irq(int irq_num, void *data)
{
uint32_t irq;
irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
return IRQ_HANDLED;
}
static irqreturn_t msm_csid_irq(int irq_num, void *data)
{
uint32_t irq;
struct csid_device *csid_dev = data;
irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
CDBG("%s CSID_IRQ_STATUS_ADDR = 0x%x\n", __func__, irq);
msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
return IRQ_HANDLED;
}
static int vpe_reset(void)
{
uint32_t vpe_version;
uint32_t rc;
vpe_reset_state_variables();
vpe_version = msm_io_r(vpe_device->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
/* disable all interrupts.*/
msm_io_w(0, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
/* clear all pending interrupts*/
msm_io_w(0x1fffff, vpe_device->vpebase + VPE_INTR_CLEAR_OFFSET);
/* write sw_reset to reset the core. */
msm_io_w(0x10, vpe_device->vpebase + VPE_SW_RESET_OFFSET);
/* then poll the reset bit, it should be self-cleared. */
while (1) {
rc =
msm_io_r(vpe_device->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
if (rc == 0)
break;
}
/* at this point, hardware is reset. Then pogram to default
values. */
msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_device->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
msm_io_w(VPE_CGC_ENABLE_VALUE,
vpe_device->vpebase + VPE_CGC_EN_OFFSET);
msm_io_w(1, vpe_device->vpebase + VPE_CMD_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_device->vpebase + VPE_OP_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_device->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
return 0;
}
static int vpe_reset(void)
{
uint32_t vpe_version;
uint32_t rc = 0;
unsigned long flags = 0;
spin_lock_irqsave(&vpe_ctrl->lock, flags);
if (vpe_ctrl->state == VPE_STATE_IDLE) {
pr_info("%s: VPE already disabled.", __func__);
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
return rc;
}
spin_unlock_irqrestore(&vpe_ctrl->lock, flags);
pr_info("%s, vpe_ctrl->state %d\n", __func__, vpe_ctrl->state);
vpe_reset_state_variables();
vpe_version = msm_io_r(vpe_ctrl->vpebase + VPE_HW_VERSION_OFFSET);
CDBG("vpe_version = 0x%x\n", vpe_version);
msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
msm_io_w(0x1fffff, vpe_ctrl->vpebase + VPE_INTR_CLEAR_OFFSET);
msm_io_w(0x10, vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET);
while (1) {
rc =
msm_io_r(vpe_ctrl->vpebase + VPE_SW_RESET_OFFSET) & 0x10;
if (rc == 0)
break;
}
msm_io_w(VPE_AXI_RD_ARB_CONFIG_VALUE,
vpe_ctrl->vpebase + VPE_AXI_RD_ARB_CONFIG_OFFSET);
msm_io_w(VPE_CGC_ENABLE_VALUE,
vpe_ctrl->vpebase + VPE_CGC_EN_OFFSET);
msm_io_w(1, vpe_ctrl->vpebase + VPE_CMD_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_OP_MODE_VALUE,
vpe_ctrl->vpebase + VPE_OP_MODE_OFFSET);
msm_io_w(VPE_DEFAULT_SCALE_CONFIG,
vpe_ctrl->vpebase + VPE_SCALE_CONFIG_OFFSET);
vpe_config_axi_default();
return rc;
}
static irqreturn_t msm_io_csi_irq(int irq_num, void *data)
{
uint32_t irq;
irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
if (irq & MIPI_IMASK_ERROR_OCCUR) {
if (irq & MIPI_IMASK_ERR_SOT)
pr_info("[CAM]msm_io_csi_irq: SOT error\n");
if (irq & MIPI_IMASK_ERR_SOT_SYNC)
pr_info("[CAM]msm_io_csi_irq: SOT SYNC error\n");
if (irq & MIPI_IMASK_CLK_CTL_ERROR)
pr_info("[CAM]msm_io_csi_irq: Clock lane ULPM mode sequence or command error\n");
if (irq & MIPI_IMASK_DATA_CTL_ERROR)
pr_info("[CAM]msm_io_csi_irq: Data lane ULPM mode sequence or command error\n");
#if 0
if (irq & MIPI_IMASK_CLK_CMM_ERROR) /* defeatured */
pr_err("[CAM]msm_io_csi_irq: Common mode error detected by PHY CLK lane\n");
if (irq & MIPI_IMASK_DATA_CMM_ERROR) /* defeatured */
pr_err("[CAM]msm_io_csi_irq: Common mode error detected by PHY data lane\n");
#endif
if (irq & MIPI_IMASK_DL0_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: An error occured while synchronizing data " \
"from PHY to VFE clock domain on data lane 0\n");
if (irq & MIPI_IMASK_DL1_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: An error occured while synchronizing data " \
"from PHY to VFE clock domain on data lane 1\n");
if (irq & MIPI_IMASK_DL2_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: An error occured while synchronizing data " \
"from PHY to VFE clock domain on data lane 2\n");
if (irq & MIPI_IMASK_DL3_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: An error occured while synchronizing data " \
"from PHY to VFE clock domain on data lane 3\n");
if (irq & MIPI_IMASK_ECC_ERROR)
pr_info("[CAM]msm_io_csi_irq: ECC error\n");
if (irq & MIPI_IMASK_CRC_ERROR)
pr_info("[CAM]msm_io_csi_irq: CRC error\n");
if (irq & MIPI_IMASK_FRAME_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: FS not paired with FE\n");
if (irq & MIPI_IMASK_ID_ERROR)
pr_info("[CAM]msm_io_csi_irq: Long packet ID not defined\n");
if (irq & MIPI_IMASK_EOT_ERROR)
pr_info("[CAM]msm_io_csi_irq: The received data is less than the value indicated by WC\n");
if (irq & MIPI_IMASK_DL0_FIFO_OVERFLOW)
pr_info("[CAM]msm_io_csi_irq: Data lane 0 FIFO overflow\n");
if (irq & MIPI_IMASK_DL1_FIFO_OVERFLOW)
pr_info("[CAM]msm_io_csi_irq: Data lane 1 FIFO overflow\n");
if (irq & MIPI_IMASK_DL2_FIFO_OVERFLOW)
pr_info("[CAM]msm_io_csi_irq: Data lane 2 FIFO overflow\n");
if (irq & MIPI_IMASK_DL3_FIFO_OVERFLOW)
pr_info("[CAM]msm_io_csi_irq: Data lane 3 FIFO overflow\n");
}
msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
return IRQ_HANDLED;
}
void msm_send_frame_to_vpe(uint32_t pyaddr, uint32_t pcbcraddr,
struct timespec *ts, int output_type)
{
uint32_t temp_pyaddr = 0, temp_pcbcraddr = 0;
CDBG("vpe input, pyaddr = 0x%x, pcbcraddr = 0x%x\n",
pyaddr, pcbcraddr);
msm_io_w(pyaddr, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w(pcbcraddr, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == VPE_STATE_ACTIVE)
CDBG(" =====VPE is busy!!! Wrong!========\n");
if (output_type != OUTPUT_TYPE_ST_R)
vpe_ctrl->ts = *ts;
if (output_type == OUTPUT_TYPE_ST_L) {
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + PAD_TO_2K(vpe_ctrl->out_w *
vpe_ctrl->out_h * 2, vpe_ctrl->pad_2k_bool);
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
vpe_ctrl->output_type = output_type;
vpe_ctrl->state = VPE_STATE_ACTIVE;
vpe_start();
}
int32_t msm_camio_3d_enable(const struct msm_camera_sensor_info *s_info)
{
int32_t val = 0, rc = 0;
char s3drw[] = "s3d_rw";
char s3dctl[] = "s3d_ctl";
struct platform_device *pdev = camio_dev;
pdev->resource = s_info->resource;
pdev->num_resources = s_info->num_resources;
s3drw_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, s3drw);
if (!s3drw_mem) {
pr_err("%s: no mem resource?\n", __func__);
return -ENODEV;
}
s3dctl_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, s3dctl);
if (!s3dctl_mem) {
pr_err("%s: no mem resource?\n", __func__);
return -ENODEV;
}
s3drw_io = request_mem_region(s3drw_mem->start,
resource_size(s3drw_mem), pdev->name);
if (!s3drw_io)
return -EBUSY;
s3d_rw = ioremap(s3drw_mem->start,
resource_size(s3drw_mem));
if (!s3d_rw) {
rc = -ENOMEM;
goto s3drw_nomem;
}
s3dctl_io = request_mem_region(s3dctl_mem->start,
resource_size(s3dctl_mem), pdev->name);
if (!s3dctl_io) {
rc = -EBUSY;
goto s3dctl_busy;
}
s3d_ctl = ioremap(s3dctl_mem->start,
resource_size(s3dctl_mem));
if (!s3d_ctl) {
rc = -ENOMEM;
goto s3dctl_nomem;
}
val = msm_io_r(s3d_rw);
msm_io_w((val | 0x200), s3d_rw);
return rc;
s3dctl_nomem:
release_mem_region(s3dctl_mem->start, resource_size(s3dctl_mem));
s3dctl_busy:
iounmap(s3d_rw);
s3drw_nomem:
release_mem_region(s3drw_mem->start, resource_size(s3drw_mem));
return rc;
}
static irqreturn_t msm_csid_irq(int irq_num, void *data)
{
uint32_t irq;
struct csid_device *csid_dev = data;
irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
CDBG("%s CSID%d_IRQ_STATUS_ADDR = 0x%x\n",
__func__, csid_dev->pdev->id, irq);
if (irq & (0x1 << CSID_RST_DONE_IRQ_BITSHIFT))
complete(&csid_dev->reset_complete);
msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
return IRQ_HANDLED;
}
int vpe_disable(void)
{
int rc = 0;
unsigned long flags = 0;
CDBG("%s: called", __func__);
spin_lock_irqsave(&vpe_ctrl->ops_lock, flags);
if (vpe_ctrl->state == VPE_STATE_IDLE) {
CDBG("%s: VPE already disabled", __func__);
spin_unlock_irqrestore(&vpe_ctrl->ops_lock, flags);
return 0;
}
vpe_ctrl->state = VPE_STATE_IDLE;
spin_unlock_irqrestore(&vpe_ctrl->ops_lock, flags);
vpe_ctrl->out_y_addr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
vpe_ctrl->out_cbcr_addr = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
free_irq(vpe_device->vpeirq, 0);
tasklet_kill(&vpe_tasklet);
rc = msm_camio_vpe_clk_disable();
return rc;
}
static int msm_csid_init(struct v4l2_subdev *sd, uint32_t *csid_version)
{
int rc = 0;
struct csid_device *csid_dev;
csid_dev = v4l2_get_subdevdata(sd);
if (csid_dev == NULL) {
rc = -ENOMEM;
return rc;
}
csid_dev->base = ioremap(csid_dev->mem->start,
resource_size(csid_dev->mem));
if (!csid_dev->base) {
rc = -ENOMEM;
return rc;
}
rc = msm_cam_clk_enable(&csid_dev->pdev->dev, csid_clk_info,
csid_dev->csid_clk, ARRAY_SIZE(csid_clk_info), 1);
if (rc < 0) {
iounmap(csid_dev->base);
csid_dev->base = NULL;
pr_err("%s: regulator enable failed\n", __func__);
goto clk_enable_failed;
}
#if DBG_CSID
enable_irq(csid_dev->irq->start);
#endif
csid_dev->hw_version =
msm_io_r(csid_dev->base + CSID_HW_VERSION_ADDR);
*csid_version = csid_dev->hw_version;
init_completion(&csid_dev->reset_complete);
rc = request_irq(csid_dev->irq->start, msm_csid_irq,
IRQF_TRIGGER_RISING, "csid", csid_dev);
msm_csid_reset(csid_dev);
pr_info("%s:%d\n", __func__, __LINE__);
return rc;
clk_enable_failed:
iounmap(csid_dev->base);
csid_dev->base = NULL;
pr_info("%s:%d\n", __func__, __LINE__);
return rc;
}
void msm_camio_camif_pad_reg_reset(void)
{
uint32_t reg;
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
msleep(10);
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
reg |= 0x3;
msm_io_w(reg, camifpadbase);
msleep(10);
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
reg |= 0x10;
msm_io_w(reg, camifpadbase);
msleep(10);
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
/* Need to be uninverted*/
reg &= 0x03;
msm_io_w(reg, camifpadbase);
msleep(10);
}
void msm_camio_disable(struct platform_device *pdev)
{
uint32_t val;
val = (0x0 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
(0x0 <<
MIPI_CALIBRATION_CONTROL_SWCAL_STRENGTH_OVERRIDE_EN_SHFT) |
(0x0 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
(0x0 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
val = (20 <<
MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
(0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
//msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
//msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(10);
val = msm_io_r(csibase + MIPI_PHY_D1_CONTROL);
val &= ~((0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT));
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
usleep_range(5000, 6000);
free_irq(camio_ext.csiirq, 0);
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
CDBG("disable clocks\n");
msm_camio_clk_disable(CAMIO_CSI0_VFE_CLK);
msm_camio_clk_disable(CAMIO_CSI0_CLK);
msm_camio_clk_disable(CAMIO_CSI1_VFE_CLK);
msm_camio_clk_disable(CAMIO_CSI1_CLK);
msm_camio_clk_disable(CAMIO_VFE_PCLK);
msm_camio_clk_disable(CAMIO_CSI0_PCLK);
msm_camio_clk_disable(CAMIO_CSI1_PCLK);
msm_camio_clk_disable(CAMIO_CSI_SRC_CLK);
msm_camio_clk_disable(CAMIO_VFE_CLK);
}
static uint32_t msm_ispif_get_cid_mask(uint8_t intftype)
{
uint32_t mask = 0;
switch (intftype) {
case PIX0:
mask = msm_io_r(ispif->base +
ISPIF_PIX_INTF_CID_MASK_ADDR);
break;
case RDI0:
mask = msm_io_r(ispif->base +
ISPIF_RDI_INTF_CID_MASK_ADDR);
break;
case RDI1:
mask = msm_io_r(ispif->base +
ISPIF_RDI_1_INTF_CID_MASK_ADDR);
break;
default:
break;
}
return mask;
}
static void msm_ispif_sel_csid_core(uint8_t intftype, uint8_t csid)
{
int rc = 0;
uint32_t data;
if (ispif->ispif_clk[intftype] == NULL) {
pr_err("%s: ispif NULL clk\n", __func__);
return;
}
rc = clk_set_rate(ispif->ispif_clk[intftype], csid);
if (rc < 0)
pr_err("%s: clk_set_rate failed %d\n", __func__, rc);
data = msm_io_r(ispif->base + ISPIF_INPUT_SEL_ADDR);
data |= csid<<(intftype*4);
msm_io_w(data, ispif->base + ISPIF_INPUT_SEL_ADDR);
}
int msm_vpe_cfg_update(void *pinfo)
{
uint32_t rot_flag, rc = 0;
struct video_crop_t *pcrop = (struct video_crop_t *)pinfo;
rot_flag = msm_io_r(vpe_device->vpebase +
VPE_OP_MODE_OFFSET) & 0xE00;
if (pinfo != NULL) {
CDBG("Crop info in2_w = %d, in2_h = %d "
"out2_h = %d out2_w = %d \n", pcrop->in2_w,
pcrop->in2_h,
pcrop->out2_h, pcrop->out2_w);
rc = vpe_update_scaler(pcrop);
}
CDBG("return rc = %d rot_flag = %d\n", rc, rot_flag);
rc |= rot_flag;
return rc;
}
