static int vpe_start(void)
{
/* enable the frame irq, bit 0 = Display list 0 ROI done */
msm_io_w(1, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
msm_io_dump(vpe_device->vpebase + 0x10000, 0x250);
/* this triggers the operation. */
msm_io_w(1, vpe_device->vpebase + VPE_DL0_START_OFFSET);
return 0;
}
void msm_camio_csi_core_reset(void)
{
uint32_t val;
val = msm_io_r(MSM_MMSS_CLK_CTL_BASE + 0x210);
msm_io_w(val | 0x1000100, MSM_MMSS_CLK_CTL_BASE + 0x210);
#if 0
val = msm_io_r(clkctl + 0x20C);
msm_io_w(val | 0x20000, clkctl + 0x20C);
#endif
}
static void vpe_do_tasklet(unsigned long data)
{
unsigned long flags;
uint32_t pyaddr, pcbcraddr, src_y, src_cbcr, temp;
struct vpe_isr_queue_cmd_type *qcmd = NULL;
CDBG("=== vpe_do_tasklet start === \n");
spin_lock_irqsave(&vpe_ctrl->tasklet_lock, flags);
qcmd = list_first_entry(&vpe_ctrl->tasklet_q,
struct vpe_isr_queue_cmd_type, list);
if (!qcmd) {
spin_unlock_irqrestore(&vpe_ctrl->tasklet_lock, flags);
return;
}
list_del(&qcmd->list);
spin_unlock_irqrestore(&vpe_ctrl->tasklet_lock, flags);
/* interrupt to be processed, *qcmd has the payload. */
if (qcmd->irq_status & 0x1) {
CDBG("vpe plane0 frame done.\n");
pyaddr =
msm_io_r(vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
pcbcraddr =
msm_io_r(vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
if (vpe_ctrl->dis_en)
pcbcraddr = vpe_ctrl->pcbcr_before_dis;
src_y =
msm_io_r(vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
src_cbcr =
msm_io_r(vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
msm_io_w(src_y,
vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
msm_io_w(src_cbcr,
vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
temp = msm_io_r(
vpe_device->vpebase + VPE_OP_MODE_OFFSET) & 0xFFFFFFFC;
msm_io_w(temp, vpe_device->vpebase + VPE_OP_MODE_OFFSET);
CDBG("vpe send out msg.\n");
/* now pass this frame to msm_camera.c. */
vpe_send_outmsg(MSG_ID_VPE_OUTPUT_V, pyaddr, pcbcraddr);
vpe_ctrl->state = 0; /* put it back to idle. */
}
kfree(qcmd);
}
void msm_send_frame_to_vpe(uint32_t pyaddr, uint32_t pcbcraddr,
struct timespec *ts, int output_type)
{
uint32_t temp_pyaddr = 0, temp_pcbcraddr = 0;
CDBG("[CAM] vpe input, pyaddr = 0x%x, pcbcraddr = 0x%x\n",
pyaddr, pcbcraddr);
msm_io_w(pyaddr, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w(pcbcraddr, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == 1)
pr_err("[CAM] =====VPE is busy!!! Wrong!========\n");
if (output_type != OUTPUT_TYPE_ST_R)
vpe_ctrl->ts = *ts;
if (output_type == OUTPUT_TYPE_ST_L) {
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
if (vpe_ctrl->frame_pack == TOP_DOWN_FULL)
temp_pcbcraddr = temp_pyaddr + (vpe_ctrl->out_w * vpe_ctrl->out_h * 2);
else if ((vpe_ctrl->frame_pack == SIDE_BY_SIDE_HALF) ||
(vpe_ctrl->frame_pack == SIDE_BY_SIDE_FULL))
temp_pcbcraddr = temp_pyaddr +
PAD_TO_2K((vpe_ctrl->out_w * 2) * vpe_ctrl->out_h,
vpe_ctrl->pad_2k_bool);
else
CDBG("[CAM] %s: Invalid Frame Packing = %d\n", __func__,
vpe_ctrl->frame_pack);
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
vpe_ctrl->output_type = output_type;
vpe_ctrl->state = 1;
vpe_start();
}
static void msm_camio_csi_disable(void)
{
uint32_t val;
val = 0x0;
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(10);
val = msm_io_r(csibase + MIPI_PHY_D1_CONTROL);
val &= ~((0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT));
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
usleep_range(5000, 6000);
msm_io_w(0x0, csibase + MIPI_INTERRUPT_MASK);
msm_io_w(0x0, csibase + MIPI_INTERRUPT_STATUS);
csi_free_irq();
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
}
static void vpe_config_axi_default(void)
{
msm_io_w(0x25, vpe_ctrl->vpebase + VPE_AXI_ARB_2_OFFSET);
CDBG("%s: yaddr %ld cbcraddr %ld", __func__,
vpe_ctrl->out_y_addr, vpe_ctrl->out_cbcr_addr);
if (!vpe_ctrl->out_y_addr || !vpe_ctrl->out_cbcr_addr)
return;
msm_io_w(vpe_ctrl->out_y_addr,
vpe_ctrl->vpebase + VPE_OUTP0_ADDR_OFFSET);
msm_io_w(vpe_ctrl->out_cbcr_addr,
vpe_ctrl->vpebase + VPE_OUTP1_ADDR_OFFSET);
}
void msm_camio_disable(struct platform_device *pdev)
{
uint32_t val;
val = (0x0 << MIPI_CALIBRATION_CONTROL_SWCAL_CAL_EN_SHFT) |
(0x0 <<
MIPI_CALIBRATION_CONTROL_SWCAL_STRENGTH_OVERRIDE_EN_SHFT) |
(0x0 << MIPI_CALIBRATION_CONTROL_CAL_SW_HW_MODE_SHFT) |
(0x0 << MIPI_CALIBRATION_CONTROL_MANUAL_OVERRIDE_EN_SHFT);
CDBG("%s MIPI_CALIBRATION_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_CALIBRATION_CONTROL);
val = (20 <<
MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
(0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
//msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
//msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(10);
val = msm_io_r(csibase + MIPI_PHY_D1_CONTROL);
val &= ~((0x1 << MIPI_PHY_D1_CONTROL_MIPI_CLK_PHY_SHUTDOWNB_SHFT) |
(0x1 << MIPI_PHY_D1_CONTROL_MIPI_DATA_PHY_SHUTDOWNB_SHFT));
CDBG("%s MIPI_PHY_D1_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL);
usleep_range(5000, 6000);
free_irq(camio_ext.csiirq, 0);
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
CDBG("disable clocks\n");
msm_camio_clk_disable(CAMIO_CSI0_VFE_CLK);
msm_camio_clk_disable(CAMIO_CSI0_CLK);
msm_camio_clk_disable(CAMIO_CSI1_VFE_CLK);
msm_camio_clk_disable(CAMIO_CSI1_CLK);
msm_camio_clk_disable(CAMIO_VFE_PCLK);
msm_camio_clk_disable(CAMIO_CSI0_PCLK);
msm_camio_clk_disable(CAMIO_CSI1_PCLK);
msm_camio_clk_disable(CAMIO_CSI_SRC_CLK);
msm_camio_clk_disable(CAMIO_VFE_CLK);
}
void msm_camio_camif_pad_reg_reset_2(void)
{
uint32_t reg;
uint32_t mask, value;
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 1 << CAM_PAD_REG_SW_RESET_SHFT;
msm_io_w((reg & (~mask)) | (value & mask), camifpadbase);
mdelay(10);
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
mask = CAM_PAD_REG_SW_RESET_BMSK;
value = 0 << CAM_PAD_REG_SW_RESET_SHFT;
msm_io_w((reg & (~mask)) | (value & mask), camifpadbase);
mdelay(10);
}
static irqreturn_t msm_csid_irq(int irq_num, void *data)
{
uint32_t irq;
struct csid_device *csid_dev = data;
irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
CDBG("%s CSID_IRQ_STATUS_ADDR = 0x%x\n", __func__, irq);
msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
if (irq & 0x100) {
printk(KERN_DEBUG "Long p.c.: %x, short : %x\n",
msm_io_r(csid_dev->base + 0x74),
msm_io_r(csid_dev->base + 0x70));
msm_io_w(0x19 , csid_dev->base + 0x08);
}
return IRQ_HANDLED;
}
static int msm_csid_cid_lut(
struct msm_camera_csid_lut_params *csid_lut_params,
void __iomem *csidbase)
{
int rc = 0, i = 0;
uint32_t val = 0;
for (i = 0; i < csid_lut_params->num_cid && i < 4; i++) {
if (csid_lut_params->vc_cfg[i].dt < 0x12 ||
csid_lut_params->vc_cfg[i].dt > 0x37) {
CDBG("%s: unsupported data type 0x%x\n",
__func__, csid_lut_params->vc_cfg[i].dt);
return rc;
}
val = msm_io_r(csidbase + CSID_CID_LUT_VC_0_ADDR +
(csid_lut_params->vc_cfg[i].cid >> 2) * 4)
& ~(0xFF << csid_lut_params->vc_cfg[i].cid * 8);
val |= csid_lut_params->vc_cfg[i].dt <<
csid_lut_params->vc_cfg[i].cid * 8;
msm_io_w(val, csidbase + CSID_CID_LUT_VC_0_ADDR +
(csid_lut_params->vc_cfg[i].cid >> 2) * 4);
val = csid_lut_params->vc_cfg[i].decode_format << 4 | 0x3;
msm_io_w(val, csidbase + CSID_CID_n_CFG_ADDR +
(csid_lut_params->vc_cfg[i].cid * 4));
}
return rc;
}
static int msm_csid_config(struct csid_cfg_params *cfg_params)
{
int rc = 0;
uint32_t val = 0;
struct csid_device *csid_dev;
struct msm_camera_csid_params *csid_params;
void __iomem *csidbase;
csid_dev = v4l2_get_subdevdata(cfg_params->subdev);
csidbase = csid_dev->base;
if (csidbase == NULL)
return -ENOMEM;
csid_params = cfg_params->parms;
val = csid_params->lane_cnt - 1;
val |= csid_params->lane_assign << 2;
val |= 0x1 << 10;
val |= 0x1 << 11;
val |= 0x1 << 12;
val |= 0x1 << 13;
val |= 0x1 << 28;
msm_io_w(val, csidbase + CSID_CORE_CTRL_ADDR);
rc = msm_csid_cid_lut(&csid_params->lut_params, csidbase);
if (rc < 0)
return rc;
msm_csid_set_debug_reg(csidbase, csid_params);
return rc;
}
void msm_camio_mode_config(enum msm_cam_mode mode)
{
uint32_t val;
val = msm_io_r(s3d_ctl);
if (mode == MODE_DUAL) {
msm_io_w(val | 0x3, s3d_ctl);
} else if (mode == MODE_L) {
msm_io_w(((val | 0x2) & ~(0x1)), s3d_ctl);
val = msm_io_r(s3d_ctl);
CDBG("the camio mode config left value is %d\n", val);
} else {
msm_io_w(((val | 0x1) & ~(0x2)), s3d_ctl);
val = msm_io_r(s3d_ctl);
CDBG("the camio mode config right value is %d\n", val);
}
}
void msm_vpe_offset_update(int frame_pack, uint32_t pyaddr, uint32_t pcbcraddr,
struct timespec *ts, int output_id, struct msm_st_half st_half,
int frameid)
{
struct msm_vpe_buf_info vpe_buf;
uint32_t input_stride;
vpe_buf.vpe_crop.in2_w = st_half.stCropInfo.in_w;
vpe_buf.vpe_crop.in2_h = st_half.stCropInfo.in_h;
vpe_buf.vpe_crop.out2_w = st_half.stCropInfo.out_w;
vpe_buf.vpe_crop.out2_h = st_half.stCropInfo.out_h;
vpe_ctrl->dis_offset.dis_offset_x = st_half.pix_x_off;
vpe_ctrl->dis_offset.dis_offset_y = st_half.pix_y_off;
vpe_ctrl->dis_offset.frame_id = frameid;
vpe_ctrl->frame_pack = frame_pack;
vpe_ctrl->output_type = output_id;
input_stride = (st_half.buf_cbcr_stride * (1<<16)) +
st_half.buf_y_stride;
msm_io_w(input_stride, vpe_device->vpebase + VPE_SRC_YSTRIDE1_OFFSET);
vpe_update_scaler_with_dis(&(vpe_buf.vpe_crop),
&(vpe_ctrl->dis_offset));
msm_send_frame_to_vpe(pyaddr, pcbcraddr, ts, output_id);
}
static irqreturn_t msm_io_csi_irq(int irq_num, void *data)
{
uint32_t irq;
irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
return IRQ_HANDLED;
}
static void msm_camio_csi_disable(void)
{
uint32_t val;
val = 0x0;
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
usleep_range(9000, 10000);
free_irq(camio_ext.csiirq, 0);
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
}
int msm_camio_csi_enable_lp_rec(int lane_cnt)
{
int rc = 0;
uint32_t val = 0;
pr_info("[CAM] msm_camio_csi_enable_lp_rec");
val = (settle_cnt <<
MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
(hs_impedence_shift << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("[CAM] %s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
/*HTC_START Horng 20110802*/
/*Disable MIPI lane2,lane3 if not in use*/
if (lane_cnt > 2) {
msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
} else {
msm_io_w(0x00000000, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(0x00000000, csibase + MIPI_PHY_D3_CONTROL2);
}
/*HTC_END*/
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x1 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("[CAM] %s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
return rc;
}
static irqreturn_t msm_csiphy_irq(int irq_num, void *data)
{
uint32_t irq;
struct csiphy_device *csiphy_dev = data;
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS0_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR0_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS0 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS1_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR1_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS1 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS2_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR2_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS2 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS3_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR3_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS3 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
irq = msm_io_r(csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_STATUS4_ADDR);
msm_io_w(irq, csiphy_dev->base + MIPI_CSIPHY_INTERRUPT_CLEAR4_ADDR);
CDBG("%s MIPI_CSIPHY%d_INTERRUPT_STATUS4 = 0x%x\n",
__func__, csiphy_dev->pdev->id, irq);
msm_io_w(0x1, csiphy_dev->base + 0x164);
msm_io_w(0x0, csiphy_dev->base + 0x164);
return IRQ_HANDLED;
}
void msm_camio_3d_disable(void)
{
int32_t val = 0;
msm_io_w((val & ~0x200), s3d_rw);
iounmap(s3d_ctl);
release_mem_region(s3dctl_mem->start, resource_size(s3dctl_mem));
iounmap(s3d_rw);
release_mem_region(s3drw_mem->start, resource_size(s3drw_mem));
}
static irqreturn_t msm_csid_irq(int irq_num, void *data)
{
uint32_t irq;
struct csid_device *csid_dev = data;
irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
CDBG("%s CSID_IRQ_STATUS_ADDR = 0x%x\n", __func__, irq);
msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
return IRQ_HANDLED;
}
static int vpe_start(void)
{
#ifdef CONFIG_CAMERA_3D
struct msm_sync *sync = (struct msm_sync *)vpe_ctrl->syncdata;
#endif
/* enable the frame irq, bit 0 = Display list 0 ROI done */
msm_io_w(1, vpe_device->vpebase + VPE_INTR_ENABLE_OFFSET);
#ifdef CONFIG_CAMERA_3D
if ((atomic_read(&sync->stereo_snap_state) == STEREO_SNAP_BUFFER1_PROCESSING) ||
(atomic_read(&sync->stereo_snap_state) == STEREO_SNAP_BUFFER2_PROCESSING))
#endif
msm_io_dump(vpe_device->vpebase + 0x10000, 0x250);
/* this triggers the operation. */
msm_io_w(1, vpe_device->vpebase + VPE_DL0_START_OFFSET);
return 0;
}
static irqreturn_t msm_io_csi_irq(int irq_num, void *data)
{
uint32_t irq;
irq = msm_io_r(csibase + MIPI_INTERRUPT_STATUS);
CDBG("%s MIPI_INTERRUPT_STATUS = 0x%x\n", __func__, irq);
if (irq & MIPI_IMASK_ERROR_OCCUR) {
if (irq & MIPI_IMASK_ERR_SOT)
pr_info("[CAM]msm_io_csi_irq: SOT error\n");
if (irq & MIPI_IMASK_ERR_SOT_SYNC)
pr_info("[CAM]msm_io_csi_irq: SOT SYNC error\n");
if (irq & MIPI_IMASK_CLK_CTL_ERROR)
pr_info("[CAM]msm_io_csi_irq: Clock lane ULPM mode sequence or command error\n");
if (irq & MIPI_IMASK_DATA_CTL_ERROR)
pr_info("[CAM]msm_io_csi_irq: Data lane ULPM mode sequence or command error\n");
#if 0
if (irq & MIPI_IMASK_CLK_CMM_ERROR) /* defeatured */
pr_err("[CAM]msm_io_csi_irq: Common mode error detected by PHY CLK lane\n");
if (irq & MIPI_IMASK_DATA_CMM_ERROR) /* defeatured */
pr_err("[CAM]msm_io_csi_irq: Common mode error detected by PHY data lane\n");
#endif
if (irq & MIPI_IMASK_DL0_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: An error occured while synchronizing data " \
"from PHY to VFE clock domain on data lane 0\n");
if (irq & MIPI_IMASK_DL1_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: An error occured while synchronizing data " \
"from PHY to VFE clock domain on data lane 1\n");
if (irq & MIPI_IMASK_DL2_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: An error occured while synchronizing data " \
"from PHY to VFE clock domain on data lane 2\n");
if (irq & MIPI_IMASK_DL3_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: An error occured while synchronizing data " \
"from PHY to VFE clock domain on data lane 3\n");
if (irq & MIPI_IMASK_ECC_ERROR)
pr_info("[CAM]msm_io_csi_irq: ECC error\n");
if (irq & MIPI_IMASK_CRC_ERROR)
pr_info("[CAM]msm_io_csi_irq: CRC error\n");
if (irq & MIPI_IMASK_FRAME_SYNC_ERROR)
pr_info("[CAM]msm_io_csi_irq: FS not paired with FE\n");
if (irq & MIPI_IMASK_ID_ERROR)
pr_info("[CAM]msm_io_csi_irq: Long packet ID not defined\n");
if (irq & MIPI_IMASK_EOT_ERROR)
pr_info("[CAM]msm_io_csi_irq: The received data is less than the value indicated by WC\n");
if (irq & MIPI_IMASK_DL0_FIFO_OVERFLOW)
pr_info("[CAM]msm_io_csi_irq: Data lane 0 FIFO overflow\n");
if (irq & MIPI_IMASK_DL1_FIFO_OVERFLOW)
pr_info("[CAM]msm_io_csi_irq: Data lane 1 FIFO overflow\n");
if (irq & MIPI_IMASK_DL2_FIFO_OVERFLOW)
pr_info("[CAM]msm_io_csi_irq: Data lane 2 FIFO overflow\n");
if (irq & MIPI_IMASK_DL3_FIFO_OVERFLOW)
pr_info("[CAM]msm_io_csi_irq: Data lane 3 FIFO overflow\n");
}
msm_io_w(irq, csibase + MIPI_INTERRUPT_STATUS);
return IRQ_HANDLED;
}
int vpe_config_axi(struct axidata *ad)
{
uint32_t p1;
struct msm_pmem_region *regp1 = NULL;
CDBG("vpe_config_axi:bufnum1 = %d.\n", ad->bufnum1);
if (ad->bufnum1 != 1)
return -EINVAL;
regp1 = &(ad->region[0]);
/* for video Y address */
p1 = (regp1->paddr + regp1->info.y_off);
msm_io_w(p1, vpe_device->vpebase + VPE_OUTP0_ADDR_OFFSET);
/* for video CbCr address */
p1 = (regp1->paddr + regp1->info.cbcr_off);
msm_io_w(p1, vpe_device->vpebase + VPE_OUTP1_ADDR_OFFSET);
return 0;
}
void msm_camio_disable(struct platform_device *pdev)
{
struct msm_camera_sensor_info *sinfo = pdev->dev.platform_data;
struct msm_camera_device_platform_data *camdev = sinfo->pdata;
if (!sinfo->csi_if) {
msm_camio_clk_disable(CAMIO_VFE_CAMIF_CLK);
iounmap(camifpadbase);
release_mem_region(camio_ext.camifpadphy, camio_ext.camifpadsz);
} else {
uint32_t val;
val = (20 << MIPI_PHY_D0_CONTROL2_SETTLE_COUNT_SHFT) |
(0x0F << MIPI_PHY_D0_CONTROL2_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_D0_CONTROL2_LP_REC_EN_SHFT) |
(0x1 << MIPI_PHY_D0_CONTROL2_ERR_SOT_HS_EN_SHFT);
CDBG("%s MIPI_PHY_D0_CONTROL2 val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_D0_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D1_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D2_CONTROL2);
msm_io_w(val, csibase + MIPI_PHY_D3_CONTROL2);
val = (0x0F << MIPI_PHY_CL_CONTROL_HS_TERM_IMP_SHFT) |
(0x0 << MIPI_PHY_CL_CONTROL_LP_REC_EN_SHFT);
CDBG("%s MIPI_PHY_CL_CONTROL val=0x%x\n", __func__, val);
msm_io_w(val, csibase + MIPI_PHY_CL_CONTROL);
msleep(10);
free_irq(camio_ext.csiirq, 0);
msm_camio_clk_disable(CAMIO_CSI_PCLK);
msm_camio_clk_disable(CAMIO_CSI_VFE_CLK);
msm_camio_clk_disable(CAMIO_CSI_CLK);
iounmap(csibase);
release_mem_region(camio_ext.csiphy, camio_ext.csisz);
}
CDBG("disable clocks\n");
msm_camio_clk_disable(CAMIO_VFE_CLK);
msm_camio_clk_disable(CAMIO_CAM_MCLK_CLK);
msm_camio_clk_disable(CAMIO_CAMIF_PAD_PBDG_CLK);
msm_camio_clk_disable(CAMIO_VFE_PBDG_CLK);
camdev->camera_gpio_off();
}
void msm_send_frame_to_vpe(uint32_t pyaddr, uint32_t pcbcraddr,
struct timespec *ts, int output_type)
{
uint32_t temp_pyaddr = 0, temp_pcbcraddr = 0;
CDBG("vpe input, pyaddr = 0x%x, pcbcraddr = 0x%x\n",
pyaddr, pcbcraddr);
msm_io_w(pyaddr, vpe_device->vpebase + VPE_SRCP0_ADDR_OFFSET);
msm_io_w(pcbcraddr, vpe_device->vpebase + VPE_SRCP1_ADDR_OFFSET);
if (vpe_ctrl->state == VPE_STATE_ACTIVE)
CDBG(" =====VPE is busy!!! Wrong!========\n");
if (output_type != OUTPUT_TYPE_ST_R)
vpe_ctrl->ts = *ts;
if (output_type == OUTPUT_TYPE_ST_L) {
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + PAD_TO_2K(vpe_ctrl->out_w *
vpe_ctrl->out_h * 2, vpe_ctrl->pad_2k_bool);
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
if (vpe_ctrl->dis_en) {
/* Changing the VPE output CBCR address,
to make Y/CBCR continuous */
vpe_ctrl->pcbcr_before_dis = msm_io_r(vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
temp_pyaddr = msm_io_r(vpe_device->vpebase +
VPE_OUTP0_ADDR_OFFSET);
temp_pcbcraddr = temp_pyaddr + vpe_ctrl->pcbcr_dis_offset;
msm_io_w(temp_pcbcraddr, vpe_device->vpebase +
VPE_OUTP1_ADDR_OFFSET);
}
vpe_ctrl->output_type = output_type;
vpe_ctrl->state = VPE_STATE_ACTIVE;
vpe_start();
}
int32_t msm_camio_3d_enable(const struct msm_camera_sensor_info *s_info)
{
int32_t val = 0, rc = 0;
char s3drw[] = "s3d_rw";
char s3dctl[] = "s3d_ctl";
struct platform_device *pdev = camio_dev;
pdev->resource = s_info->resource;
pdev->num_resources = s_info->num_resources;
s3drw_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, s3drw);
if (!s3drw_mem) {
pr_err("%s: no mem resource?\n", __func__);
return -ENODEV;
}
s3dctl_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, s3dctl);
if (!s3dctl_mem) {
pr_err("%s: no mem resource?\n", __func__);
return -ENODEV;
}
s3drw_io = request_mem_region(s3drw_mem->start,
resource_size(s3drw_mem), pdev->name);
if (!s3drw_io)
return -EBUSY;
s3d_rw = ioremap(s3drw_mem->start,
resource_size(s3drw_mem));
if (!s3d_rw) {
rc = -ENOMEM;
goto s3drw_nomem;
}
s3dctl_io = request_mem_region(s3dctl_mem->start,
resource_size(s3dctl_mem), pdev->name);
if (!s3dctl_io) {
rc = -EBUSY;
goto s3dctl_busy;
}
s3d_ctl = ioremap(s3dctl_mem->start,
resource_size(s3dctl_mem));
if (!s3d_ctl) {
rc = -ENOMEM;
goto s3dctl_nomem;
}
val = msm_io_r(s3d_rw);
msm_io_w((val | 0x200), s3d_rw);
return rc;
s3dctl_nomem:
release_mem_region(s3dctl_mem->start, resource_size(s3dctl_mem));
s3dctl_busy:
iounmap(s3d_rw);
s3drw_nomem:
release_mem_region(s3drw_mem->start, resource_size(s3drw_mem));
return rc;
}
static irqreturn_t vpe_parse_irq(int irq_num, void *data)
{
vpe_ctrl->irq_status = msm_io_r_mb(vpe_ctrl->vpebase +
VPE_INTR_STATUS_OFFSET);
msm_io_w_mb(vpe_ctrl->irq_status, vpe_ctrl->vpebase +
VPE_INTR_CLEAR_OFFSET);
msm_io_w(0, vpe_ctrl->vpebase + VPE_INTR_ENABLE_OFFSET);
CDBG("%s: vpe_parse_irq =0x%x.\n", __func__, vpe_ctrl->irq_status);
tasklet_schedule(&vpe_tasklet);
return IRQ_HANDLED;
}
static int msm_csiphy_release(struct v4l2_subdev *sd)
{
struct csiphy_device *csiphy_dev;
int i;
csiphy_dev = v4l2_get_subdevdata(sd);
for (i = 0; i < 4; i++)
msm_io_w(0x0, csiphy_dev->base +
MIPI_CSIPHY_LNn_CFG2_ADDR + 0x40*i);
msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_LNCK_CFG2_ADDR);
msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_PWR_CFG_ADDR);
#if DBG_CSIPHY
disable_irq(csiphy_dev->irq->start);
#endif
msm_cam_clk_enable(&csiphy_dev->pdev->dev, csiphy_clk_info,
csiphy_dev->csiphy_clk, ARRAY_SIZE(csiphy_clk_info), 0);
iounmap(csiphy_dev->base);
return 0;
}
static irqreturn_t msm_csid_irq(int irq_num, void *data)
{
uint32_t irq;
struct csid_device *csid_dev = data;
irq = msm_io_r(csid_dev->base + CSID_IRQ_STATUS_ADDR);
CDBG("%s CSID%d_IRQ_STATUS_ADDR = 0x%x\n",
__func__, csid_dev->pdev->id, irq);
if (irq & (0x1 << CSID_RST_DONE_IRQ_BITSHIFT))
complete(&csid_dev->reset_complete);
msm_io_w(irq, csid_dev->base + CSID_IRQ_CLEAR_CMD_ADDR);
return IRQ_HANDLED;
}
static int msm_csiphy_release(struct v4l2_subdev *sd)
{
struct csiphy_device *csiphy_dev;
int i;
csiphy_dev = v4l2_get_subdevdata(sd);
for (i = 0; i < 4; i++)
msm_io_w(0x0, csiphy_dev->base +
MIPI_CSIPHY_LNn_CFG2_ADDR + 0x40*i);
msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_LNCK_CFG2_ADDR);
msm_io_w(0x0, csiphy_dev->base + MIPI_CSIPHY_GLBL_PWR_CFG_ADDR);
#if DBG_CSIPHY
disable_irq(csiphy_dev->irq->start);
#endif
msm_cam_clk_enable(&csiphy_dev->pdev->dev, csiphy_clk_info,
csiphy_dev->csiphy_clk, ARRAY_SIZE(csiphy_clk_info), 0);
iounmap(csiphy_dev->base);
csiphy_dev->base = NULL; /* LGE_CHANGE, Assign Null to unmapped addresses, 2012-05-14, [email protected] */
return 0;
}
void msm_camio_camif_pad_reg_reset(void)
{
uint32_t reg;
msm_camio_clk_sel(MSM_CAMIO_CLK_SRC_INTERNAL);
msleep(10);
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
reg |= 0x3;
msm_io_w(reg, camifpadbase);
msleep(10);
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
reg |= 0x10;
msm_io_w(reg, camifpadbase);
msleep(10);
reg = (msm_io_r(camifpadbase)) & CAMIF_CFG_RMSK;
/* Need to be uninverted*/
reg &= 0x03;
msm_io_w(reg, camifpadbase);
msleep(10);
}
