int mt76x2u_mac_reset(struct mt76x02_dev *dev) { mt76_wr(dev, MT_WPDMA_GLO_CFG, BIT(4) | BIT(5)); /* init pbf regs */ mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f); mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf); mt76_write_mac_initvals(dev); mt76_wr(dev, MT_TX_LINK_CFG, 0x1020); mt76_wr(dev, MT_AUTO_RSP_CFG, 0x13); mt76_wr(dev, MT_MAX_LEN_CFG, 0x2f00); mt76_wr(dev, MT_TX_RTS_CFG, 0x92b20); mt76_wr(dev, MT_WMM_AIFSN, 0x2273); mt76_wr(dev, MT_WMM_CWMIN, 0x2344); mt76_wr(dev, MT_WMM_CWMAX, 0x34aa); mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR | MT_MAC_SYS_CTRL_RESET_BBP); if (is_mt7612(dev)) mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); mt76x2u_mac_fixup_xtal(dev); return 0; }
int mt76x2_mac_reset(struct mt76x02_dev *dev, bool hard) { const u8 *macaddr = dev->mt76.macaddr; u32 val; int i, k; if (!mt76x02_wait_for_mac(&dev->mt76)) return -ETIMEDOUT; val = mt76_rr(dev, MT_WPDMA_GLO_CFG); val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_BUSY | MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_BUSY | MT_WPDMA_GLO_CFG_DMA_BURST_SIZE); val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3); mt76_wr(dev, MT_WPDMA_GLO_CFG, val); mt76x2_mac_pbf_init(dev); mt76_write_mac_initvals(dev); mt76x2_fixup_xtal(dev); mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR | MT_MAC_SYS_CTRL_RESET_BBP); if (is_mt7612(dev)) mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000); mt76_wr(dev, MT_RF_SETTING_0, 0x08800000); usleep_range(5000, 10000); mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000); mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401); mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); mt76x02_mac_setaddr(dev, macaddr); mt76x02_init_beacon_config(dev); if (!hard) return 0; for (i = 0; i < 256 / 32; i++) mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0); for (i = 0; i < 256; i++) { mt76x02_mac_wcid_setup(dev, i, 0, NULL); mt76_wr(dev, MT_WCID_TX_RATE(i), 0); mt76_wr(dev, MT_WCID_TX_RATE(i) + 4, 0); } for (i = 0; i < MT_MAX_VIFS; i++) mt76x02_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL); for (i = 0; i < 16; i++) for (k = 0; k < 4; k++) mt76x02_mac_shared_key_setup(dev, i, k, NULL); for (i = 0; i < 16; i++) mt76_rr(dev, MT_TX_STAT_FIFO); mt76_wr(dev, MT_CH_TIME_CFG, MT_CH_TIME_CFG_TIMER_EN | MT_CH_TIME_CFG_TX_AS_BUSY | MT_CH_TIME_CFG_RX_AS_BUSY | MT_CH_TIME_CFG_NAV_AS_BUSY | MT_CH_TIME_CFG_EIFS_AS_BUSY | MT_CH_CCA_RC_EN | FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1)); mt76x02_set_tx_ackto(dev); return 0; }
int mt76_mac_reset(struct mt76_dev *dev, bool hard) { static const u8 null_addr[ETH_ALEN] = {}; u32 val; int i, k; if (!mt76_wait_for_mac(dev)) return -ETIMEDOUT; val = mt76_rr(dev, MT_WPDMA_GLO_CFG); val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_BUSY | MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_BUSY | MT_WPDMA_GLO_CFG_DMA_BURST_SIZE); val |= MT76_SET(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3); mt76_wr(dev, MT_WPDMA_GLO_CFG, val); mt76_mac_pbf_init(dev); mt76_write_mac_initvals(dev); mt76_fixup_xtal(dev); mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR | MT_MAC_SYS_CTRL_RESET_BBP); if (is_mt7612(dev)) mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000); mt76_wr(dev, MT_RF_SETTING_0, 0x08800000); msleep(5); mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000); mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401); mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr)); mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4)); mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(dev->macaddr)); mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(dev->macaddr + 4) | MT76_SET(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */ MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT); /* Fire a pre-TBTT interrupt 8 ms before TBTT */ mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT, 8 << 4); mt76_wr(dev, MT_INT_TIMER_EN, 0); mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff); if (!hard) return 0; for (i = 0; i < 256; i++) mt76_mac_wcid_setup(dev, i, 0, NULL); for (i = 0; i < 16; i++) for (k = 0; k < 4; k++) mt76_mac_shared_key_setup(dev, i, k, NULL); for (i = 0; i < 8; i++) { mt76_mac_set_bssid(dev, i, null_addr); mt76_mac_set_beacon(dev, i, NULL); } for (i = 0; i < 16; i++) mt76_rr(dev, MT_TX_STAT_FIFO); mt76_set(dev, MT_MAC_APC_BSSID_H(0), MT_MAC_APC_BSSID0_H_EN); mt76_init_beacon_offsets(dev); return 0; }
static int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard) { static const u8 null_addr[ETH_ALEN] = {}; const u8 *macaddr = dev->mt76.macaddr; u32 val; int i, k; if (!mt76x2_wait_for_mac(dev)) return -ETIMEDOUT; val = mt76_rr(dev, MT_WPDMA_GLO_CFG); val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_BUSY | MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_BUSY | MT_WPDMA_GLO_CFG_DMA_BURST_SIZE); val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3); mt76_wr(dev, MT_WPDMA_GLO_CFG, val); mt76x2_mac_pbf_init(dev); mt76_write_mac_initvals(dev); mt76x2_fixup_xtal(dev); mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR | MT_MAC_SYS_CTRL_RESET_BBP); if (is_mt7612(dev)) mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN); mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000); mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31)); mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000); mt76_wr(dev, MT_RF_SETTING_0, 0x08800000); usleep_range(5000, 10000); mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000); mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401); mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(macaddr)); mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(macaddr + 4)); mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(macaddr)); mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(macaddr + 4) | FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) | /* 8 beacons */ MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT); /* Fire a pre-TBTT interrupt 8 ms before TBTT */ mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT, 8 << 4); mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER, MT_DFS_GP_INTERVAL); mt76_wr(dev, MT_INT_TIMER_EN, 0); mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff); if (!hard) return 0; for (i = 0; i < 256 / 32; i++) mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0); for (i = 0; i < 256; i++) mt76x2_mac_wcid_setup(dev, i, 0, NULL); for (i = 0; i < MT_MAX_VIFS; i++) mt76x2_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL); for (i = 0; i < 16; i++) for (k = 0; k < 4; k++) mt76x2_mac_shared_key_setup(dev, i, k, NULL); for (i = 0; i < 8; i++) { mt76x2_mac_set_bssid(dev, i, null_addr); mt76x2_mac_set_beacon(dev, i, NULL); } for (i = 0; i < 16; i++) mt76_rr(dev, MT_TX_STAT_FIFO); mt76_wr(dev, MT_CH_TIME_CFG, MT_CH_TIME_CFG_TIMER_EN | MT_CH_TIME_CFG_TX_AS_BUSY | MT_CH_TIME_CFG_RX_AS_BUSY | MT_CH_TIME_CFG_NAV_AS_BUSY | MT_CH_TIME_CFG_EIFS_AS_BUSY | FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1)); mt76x2_init_beacon_offsets(dev); mt76x2_set_tx_ackto(dev); return 0; }