static int clk_mt2701_aud_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; int r; clk_data = mtk_alloc_clk_data(CLK_AUD_NR); mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); goto err_clk_provider; } r = devm_of_platform_populate(&pdev->dev); if (r) goto err_plat_populate; return 0; err_plat_populate: of_clk_del_provider(node); err_clk_provider: return r; }
static void __init mtk_pericfg_init(struct device_node *node) { struct clk_onecell_data *clk_data; int r; void __iomem *base; base = of_iomap(node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); return; } clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), clk_data); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, &mt8173_clk_lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); mtk_register_reset_controller(node, 2, 0); }
static int mtk_pericfg_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; void __iomem *base; int r; struct device_node *node = pdev->dev.of_node; struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data); mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, &mt7629_clk_lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) return r; clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]); return 0; }
static void __init mtk_topckgen_init(struct device_node *node) { struct clk_onecell_data *clk_data; void __iomem *base; int r; base = of_iomap(node, 0); if (!base) { pr_err("%s(): ioremap failed\n", __func__); return; } mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8173_clk_lock, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); mtk_clk_enable_critical(); }
static int mtk_topckgen_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; void __iomem *base; struct device_node *node = pdev->dev.of_node; struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt7629_clk_lock, clk_data); clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]); clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]); clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]); return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); }
static int mtk_infrasys_init(struct platform_device *pdev) { int r, i; struct device_node *node = pdev->dev.of_node; if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); } else { for (i = 0; i < CLK_INFRA_NR; i++) { if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) infra_clk_data->clks[i] = ERR_PTR(-ENOENT); } } mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), infra_clk_data); mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); if (r) return r; mtk_register_reset_controller(node, 2, 0x30); return 0; }
static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; clk_data = mtk_alloc_clk_data(CLK_IPU_CORE1_NR_CLK); mtk_clk_register_gates(node, ipu_core1_clks, ARRAY_SIZE(ipu_core1_clks), clk_data); return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); }
static int mtk_apmixedsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR); if (!clk_data) return -ENOMEM; mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls), clk_data); mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs), clk_data); return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); }
static void __init mtk_infrasys_init(struct device_node *node) { struct clk_onecell_data *clk_data; int r; clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); mtk_register_reset_controller(node, 2, 0x30); }
static int clk_mt2701_mm_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; int r; struct device_node *node = pdev->dev.of_node; clk_data = mtk_alloc_clk_data(CLK_MM_NR); mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); return r; }
static int clk_mt2712_venc_probe(struct platform_device *pdev) { struct clk_onecell_data *clk_data; int r; struct device_node *node = pdev->dev.of_node; clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r != 0) pr_err("%s(): could not register clock provider: %d\n", __func__, r); return r; }
static int mtk_apmixedsys_init(struct platform_device *pdev) { struct clk_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); if (!clk_data) return -ENOMEM; mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]); clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]); return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); }
static int mtk_infrasys_init(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; struct clk_onecell_data *clk_data; int r; clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) return r; return 0; }
static void __init mtk_infrasys_init_early(struct device_node *node) { int r, i; if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); for (i = 0; i < CLK_INFRA_NR; i++) infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); } mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", __func__, r); }