static void emsk_mux_init(void)
{
MUX_REG *mux_regs;
mux_regs = (MUX_REG *)(PERIPHERAL_BASE|REL_REGBASE_PINMUX);
mux_init(mux_regs);
/**
* + Please refer to corresponding EMSK User Guide for detailed information
* -> Appendix: A Hardware Functional Description
* -> Pmods Configuration summary
* + Set up pin-multiplexer of all PMOD connections
* - PM1 J1: Upper row as UART 0, lower row as SPI Slave
* - PM2 J2: IIC 0 and run/halt signals
* - PM3 J3: GPIO Port A and Port C
* - PM4 J4: IIC 1 and Port D
* - PM5 J5: Upper row as SPI Master, lower row as Port A
* - PM6 J6: Upper row as SPI Master, lower row as Port A
*/
set_pmod_mux(mux_regs, PM1_UR_UART_0 | PM1_LR_SPI_S \
| PM2_I2C_HRI \
| PM3_GPIO_AC \
| PM4_I2C_GPIO_D \
| PM5_UR_SPI_M1 | PM5_LR_GPIO_A \
| PM6_UR_SPI_M0 | PM6_LR_GPIO_A );
/**
* PM1 upper row as UART
* UM4:RXD, UM3:TXD
* UM2:RTS_N, UM1:CTS_N
*/
set_uart_map(mux_regs, 0xe4);
}
void mux(struct mux_func **funcv) {
struct mux_context context;
mux_init(&context, funcv);
while (mux_is_active(funcv)) {
mux_set(&context, funcv);
select(context.highest, NULL, &(context.writerv), NULL, NULL);
for ( ; *funcv; funcv++)
if (FD_ISSET((*funcv)->fd, &(context.writerv)))
(*funcv)->func(*funcv);
}
}
int32_t flextimer_setupChannelPin(struct timer *ftm, struct pwm_pin *pin) {
int32_t ret;
struct mux *mux = mux_init();
if (pin->pin == 0) {
return -1;
}
ret = mux_pinctl(mux, pin->pin, pin->ctl, VF610_PWM_GENERAL_CTRL);
if (ret < 0) {
return -1;
}
return 0;
}
void
boot(void)
{
if (warm_reset())
force_emif_self_refresh();
watchdog_init();
mux_init();
enable_uart_clocks();
cons_init();
scale_vcores();
clock_init();
sdram_init();
bzero(__bss_start, __bss_end - __bss_start);
timer_init();
storage_init();
}
void env_init(char **argv)
{
if(strcmp(argv[1], "mp") == 0) {
env = MUX;
}
else if(strcmp(argv[1], "maze") == 0) {
env = MAZE;
}
else {
printf("invalid env: %s\n", argv[1]);
exit(EXIT_FAILURE);
}
switch(env) {
case MUX:
mux_init(atoi(argv[2]));
break;
case MAZE:
maze_init(argv[2]);
break;
}
}
int __init op_nmi_init(struct oprofile_operations *ops)
{
__u8 vendor = boot_cpu_data.x86_vendor;
__u8 family = boot_cpu_data.x86;
char *cpu_type = NULL;
int ret = 0;
if (!cpu_has_apic)
return -ENODEV;
switch (vendor) {
case X86_VENDOR_AMD:
/* Needs to be at least an Athlon (or hammer in 32bit mode) */
switch (family) {
case 6:
cpu_type = "i386/athlon";
break;
case 0xf:
/*
* Actually it could be i386/hammer too, but
* give user space an consistent name.
*/
cpu_type = "x86-64/hammer";
break;
case 0x10:
cpu_type = "x86-64/family10";
break;
case 0x11:
cpu_type = "x86-64/family11h";
break;
default:
return -ENODEV;
}
model = &op_amd_spec;
break;
case X86_VENDOR_INTEL:
switch (family) {
/* Pentium IV */
case 0xf:
p4_init(&cpu_type);
break;
/* A P6-class processor */
case 6:
ppro_init(&cpu_type);
break;
default:
break;
}
if (cpu_type)
break;
if (!cpu_has_arch_perfmon)
return -ENODEV;
/* use arch perfmon as fallback */
cpu_type = "i386/arch_perfmon";
model = &op_arch_perfmon_spec;
break;
default:
return -ENODEV;
}
#ifdef CONFIG_SMP
register_cpu_notifier(&oprofile_cpu_nb);
#endif
/* default values, can be overwritten by model */
ops->create_files = nmi_create_files;
ops->setup = nmi_setup;
ops->shutdown = nmi_shutdown;
ops->start = nmi_start;
ops->stop = nmi_stop;
ops->cpu_type = cpu_type;
if (model->init)
ret = model->init(ops);
if (ret)
return ret;
if (!model->num_virt_counters)
model->num_virt_counters = model->num_counters;
mux_init(ops);
init_sysfs();
using_nmi = 1;
printk(KERN_INFO "oprofile: using NMI interrupt.\n");
return 0;
}
ADC_INIT(nxp, index, bits, hz) {
PCC_Type *pcc = PCC;
struct clock *clk = clock_init();
struct adc *adc = (struct adc *) ADC_GET_DEV(index);
struct adc_ctrl *ctrl = adc->ctrl;
struct mux *mux = mux_init();
int32_t ret;
if (adc == NULL) {
goto nxp_adc_init_error0;
}
ret = adc_generic_init(adc);
if (ret < 0) {
goto nxp_adc_init_error0;
}
/*
* Already Init
*/
if (ret > 0) {
if (bits != 0) {
/* TODO reconfigure */
}
/* return instance */
goto nxp_adc_init_out;
}
/* Clock Init */
if (!ctrl->init) {
#ifdef CONFIG_ADC_THREAD_SAVE
ctrl->lock = OS_CREATE_MUTEX_RECURSIVE(ctrl->lock);
if (!ctrl->lock) {
goto nxp_adc_init_error0;
}
#endif
/* select clock and activate clock */
pcc->PCCn[ctrl->clkIndex] = PCC_PCCn_PCS(ctrl->clkMuxing) | PCC_PCCn_CGC_MASK;
ctrl->feq = clock_getPeripherySpeed(clk, ctrl->clkID);
/* TODO ADC Contoller Init uese nxp_adc_init_error1 for exit */
adc->ctrl->init = true;
}
/* Lock Controller while setup */
CTRL_LOCK(adc, 0, NULL);
ctrl->channelInUse++;
ret = mux_pinctl(mux, adc->pin.pin, adc->pin.cfg, adc->pin.extra);
if (ret < 0) {
goto nxp_adc_init_error2;
}
/* TODO ADC Init */
CTRL_UNLOCK(adc, NULL);
nxp_adc_init_out:
return adc;
/* TODO remove goto */
goto nxp_adc_init_error1;
goto nxp_adc_init_error2;
nxp_adc_init_error2:
CTRL_UNLOCK(adc, NULL);
nxp_adc_init_error1:
if (ctrl->channelInUse <= 1) {
#ifdef CONFIG_ADC_THREAD_SAVE
vSemaphoreDelete(adc->ctrl->lock);
#endif
/* TODO Channel DeInit */
adc->ctrl->init = false;
}
ctrl->channelInUse--;
nxp_adc_init_error0:
return NULL;
}
int __init op_nmi_init(struct oprofile_operations *ops)
{
__u8 vendor = boot_cpu_data.x86_vendor;
__u8 family = boot_cpu_data.x86;
char *cpu_type = NULL;
int ret = 0;
if (!cpu_has_apic)
return -ENODEV;
if (force_cpu_type == timer)
return -ENODEV;
switch (vendor) {
case X86_VENDOR_AMD:
switch (family) {
case 6:
cpu_type = "i386/athlon";
break;
case 0xf:
cpu_type = "x86-64/hammer";
break;
case 0x10:
cpu_type = "x86-64/family10";
break;
case 0x11:
cpu_type = "x86-64/family11h";
break;
case 0x12:
cpu_type = "x86-64/family12h";
break;
case 0x14:
cpu_type = "x86-64/family14h";
break;
case 0x15:
cpu_type = "x86-64/family15h";
break;
default:
return -ENODEV;
}
model = &op_amd_spec;
break;
case X86_VENDOR_INTEL:
switch (family) {
case 0xf:
p4_init(&cpu_type);
break;
case 6:
ppro_init(&cpu_type);
break;
default:
break;
}
if (cpu_type)
break;
if (!cpu_has_arch_perfmon)
return -ENODEV;
cpu_type = "i386/arch_perfmon";
model = &op_arch_perfmon_spec;
break;
default:
return -ENODEV;
}
/* default values, can be overwritten by model */
ops->create_files = nmi_create_files;
ops->setup = nmi_setup;
ops->shutdown = nmi_shutdown;
ops->start = nmi_start;
ops->stop = nmi_stop;
ops->cpu_type = cpu_type;
if (model->init)
ret = model->init(ops);
if (ret)
return ret;
if (!model->num_virt_counters)
model->num_virt_counters = model->num_counters;
mux_init(ops);
init_suspend_resume();
printk(KERN_INFO "oprofile: using NMI interrupt.\n");
return 0;
}
