/*
* Each interrupt cause is assigned an IRQ number.
* Southbridge has 16*2 (two 8259's) interrupts.
* Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
* If multiple interrupts are pending, get_irq() returns the
* lowest pending irq number first.
*
*
* IRQ # Source Trig Active
* =============================================================
*
* Southbridge
* -----------
* IRQ # Source Trig
* =============================================================
* 0 ISA High Resolution Counter Edge
* 1 Keyboard Edge
* 2 Cascade From (IRQ 8-15) Edge
* 3 Com 2 (Uart 2) Edge
* 4 Com 1 (Uart 1) Edge
* 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
* 6 GPIO Level
* 7 LPT Edge
* 8 RTC Alarm Edge
* 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
* 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
* 11 USB2 Level
* 12 Mouse Edge
* 13 Reserved internally by Ali M1535+
* 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
* 15 COM 5/6 Level
*
* 16..112 Discovery-II...
*
* MPP28 Southbridge Edge High
*
*
* Interrupts are cascaded through to the Discovery-II.
*
* PCI ---
* \
* CPLD --> ALI1535 -------> DISCOVERY-II
* INTF MPP28
*/
static void __init ppc7d_init_irq(void)
{
int irq;
pr_debug("%s\n", __FUNCTION__);
i8259_init(0, 0);
mv64360_init_irq();
/* IRQs 5,6,9,10,11,14,15 are level sensitive */
irq_desc[5].status |= IRQ_LEVEL;
irq_desc[6].status |= IRQ_LEVEL;
irq_desc[9].status |= IRQ_LEVEL;
irq_desc[10].status |= IRQ_LEVEL;
irq_desc[11].status |= IRQ_LEVEL;
irq_desc[14].status |= IRQ_LEVEL;
irq_desc[15].status |= IRQ_LEVEL;
/* GPP28 is edge triggered */
irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL;
}
/*
* Each interrupt cause is assigned an IRQ number.
* Southbridge has 16*2 (two 8259's) interrupts.
* Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
* If multiple interrupts are pending, get_irq() returns the
* lowest pending irq number first.
*
*
* IRQ # Source Trig Active
* =============================================================
*
* Southbridge
* -----------
* IRQ # Source Trig
* =============================================================
* 0 ISA High Resolution Counter Edge
* 1 Keyboard Edge
* 2 Cascade From (IRQ 8-15) Edge
* 3 Com 2 (Uart 2) Edge
* 4 Com 1 (Uart 1) Edge
* 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
* 6 GPIO Level
* 7 LPT Edge
* 8 RTC Alarm Edge
* 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
* 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
* 11 USB2 Level
* 12 Mouse Edge
* 13 Reserved internally by Ali M1535+
* 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
* 15 COM 5/6 Level
*
* 16..112 Discovery-II...
*
* MPP28 Southbridge Edge High
*
*
* Interrupts are cascaded through to the Discovery-II.
*
* PCI ---
* \
* CPLD --> ALI1535 -------> DISCOVERY-II
* INTF MPP28
*/
static void __init ppc7d_init_irq(void)
{
int irq;
pr_debug("%s\n", __FUNCTION__);
i8259_init(0);
mv64360_init_irq();
/* IRQ 0..15 are handled by the cascaded 8259's of the Ali1535 */
for (irq = 0; irq < 16; irq++) {
irq_desc[irq].handler = &i8259_pic;
}
/* IRQs 5,6,9,10,11,14,15 are level sensitive */
irq_desc[5].status |= IRQ_LEVEL;
irq_desc[6].status |= IRQ_LEVEL;
irq_desc[9].status |= IRQ_LEVEL;
irq_desc[10].status |= IRQ_LEVEL;
irq_desc[11].status |= IRQ_LEVEL;
irq_desc[14].status |= IRQ_LEVEL;
irq_desc[15].status |= IRQ_LEVEL;
/* GPP28 is edge triggered */
irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL;
}
