MV_STATUS mvNfpFibRuleAdd(int family, NFP_RULE_FIB *fib2)
{
MV_U32 hash;
NFP_RULE_FIB *fib;
fib = mvNfpFibLookup(family, fib2->srcL3, fib2->dstL3);
if (fib) {
MV_U32 ref = fib->ref;
mvOsMemcpy(fib, fib2, sizeof(NFP_RULE_FIB));
fib->ref = ref;
goto out;
}
hash = mv_jhash_2addr(family, fib2->srcL3, fib2->dstL3, (u32) 0, mgr_rule_jhash_iv);
hash &= NFP_FIB_HASH_MASK;
fib = (NFP_RULE_FIB *) mvOsMalloc(sizeof(NFP_RULE_FIB));
if (!fib) {
mvOsPrintf("%s: NFP (fib) OOM\n", __func__);
return MV_FAIL;
}
mvOsMemcpy(fib, fib2, sizeof(NFP_RULE_FIB));
#if 0
/* Update FIB rule from Bridge DB if needed */
if (fib->flags & NFP_F_INV) {
if (fib->flags & NFP_F_BRIDGE) {
/* lookup bridge database */
bridge = mvNfpBridgeLookup(fib->bridgeOut, fib->da);
if (bridge) {
fib->flags &= ~NFP_F_INV;
/* copy MH + outport + outdev from bridge */
fib->mh = bridge->mh_out;
fib->outport = bridge->outport;
fib->outdev = bridge->outdev;
}
}
}
#endif
fib->next = fib_hash[hash];
fib_hash[hash] = fib;
out:
NFP_DBG("NFP (fib) add %p\n", fib);
#ifdef NFP_PNC
if ((fib->flags & NFP_F_INV) == 0)
mvNfpPncFibAdd(fib);
#endif
return MV_OK;
}
MV_STATUS mvFpFdbRuleSet(MV_FP_FDB_RULE *newrule)
{
int depth = 0;
MV_U32 hash;
MV_FP_FDB_RULE* rule;
/* ignore foreign ifindex */
if (newrule->fdbInfo.ifIndex >= ETH_FP_IFINDEX_MAX)
return MV_OUT_OF_RANGE;
hash = mvFpFdbRuleHash(newrule);
hash &= (fdbRuleDbSize - 1);
rule = fdbRuleDb[hash].ruleChain;
while (rule) {
if (!mvFpFdbRuleCmp(&rule->fdbInfo, &newrule->fdbInfo))
{
fdbRuleUpdateCount++;
goto out;
}
depth++;
rule = rule->next;
}
fdbRuleSetCount++;
if(depth > fdbHashMaxDepth)
fdbHashMaxDepth = depth;
rule = mvOsMalloc(sizeof(MV_FP_FDB_RULE));
if (!rule) {
mvOsPrintf("NFP (fdb): can't allocate new rule\n");
return MV_FAIL;
}
/* FIXME: No spinlocks */
rule->next = fdbRuleDb[hash].ruleChain;
fdbRuleDb[hash].ruleChain = rule;
out:
mvOsMemcpy(rule, newrule, sizeof(MV_FP_FDB_RULE));
if (rule->fdbInfo.flags & MV_FP_FDB_IS_LOCAL) {
fdbMember[rule->fdbInfo.ifIndex] = rule->fdbInfo.bridge;
fdbMember[rule->fdbInfo.bridge] = rule->fdbInfo.bridge;
}
MV_NFP_DBG("NFP (fdb): new bridge=%d ifIndex=%d %02X:%02X:%02X:%02X:%02X:%02X flags=%x\n",
rule->fdbInfo.bridge, rule->fdbInfo.ifIndex,
rule->fdbInfo.mac[0], rule->fdbInfo.mac[1], rule->fdbInfo.mac[2],
rule->fdbInfo.mac[3], rule->fdbInfo.mac[4], rule->fdbInfo.mac[5],
rule->fdbInfo.flags);
return MV_OK;
}
MV_STATUS mvNfpBridgeRuleAdd(NFP_RULE_BRIDGE *rule2)
{
MV_U32 hash;
NFP_RULE_BRIDGE *rule;
hash = mvNfpBridgeRuleHash(rule2->bridgeId, rule2->mac);
hash &= NFP_BRIDGE_HASH_MASK;
rule = nfp_bridge_hash[hash];
while (rule) {
if (mvNfpBridgeRuleCmp(rule2->bridgeId, rule2->mac, rule)) {
MV_U32 age = rule->age;
/* Update rule, but save age */
mvOsMemcpy(rule, rule2, sizeof(NFP_RULE_BRIDGE));
rule->age = age;
goto out;
}
rule = rule->next;
}
rule = (NFP_RULE_BRIDGE *)mvOsMalloc(sizeof(NFP_RULE_BRIDGE));
if (!rule) {
mvOsPrintf("NFP (bridge) %s OOM\n", __func__);
return MV_FAIL;
}
mvOsMemcpy(rule, rule2, sizeof(NFP_RULE_BRIDGE));
rule->next = nfp_bridge_hash[hash];
nfp_bridge_hash[hash] = rule;
/* lookup incomplete FIB entries */
out:
NFP_DBG("NFP (bridge) add %p\n", rule);
return MV_OK;
}
MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType, MV_PEX_HAL_DATA *halData)
{
MV_PEX_MODE pexMode;
MV_U32 regVal;
MV_U32 status;
mvOsMemcpy(&pexHalData[pexIf], halData, sizeof(MV_PEX_HAL_DATA));
if (mvPexModeGet(pexIf, &pexMode) != MV_OK) {
mvOsPrintf("PEX init ERR. mvPexModeGet failed (pexType=%d)\n", pexMode.pexType);
return MV_ERROR;
}
if (pexMode.pexLinkUp == MV_FALSE) {
/* interface detected no Link. */
return MV_NO_SUCH;
}
/* Check that required PEX type is the one set in reset time */
if (pexType != pexMode.pexType) {
/* No Link. Shut down the Phy */
mvPexPhyPowerDown(pexIf);
mvOsPrintf("PEX init ERR. PEX type sampled mismatch (%d,%d)\n", pexType, pexMode.pexType);
return MV_ERROR;
}
if (MV_PEX_ROOT_COMPLEX == pexType) {
mvPexLocalBusNumSet(pexIf, PEX_HOST_BUS_NUM(pexIf));
mvPexLocalDevNumSet(pexIf, PEX_HOST_DEV_NUM(pexIf));
/* Local device master Enable */
mvPexMasterEnable(pexIf, MV_TRUE);
/* Local device slave Enable */
mvPexSlaveEnable(pexIf, mvPexLocalBusNumGet(pexIf), mvPexLocalDevNumGet(pexIf), MV_TRUE);
/* Interrupt disable */
status = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND));
status |= PXSAC_INT_DIS;
MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), status);
} else {
regVal = MV_REG_READ(PEX_DBG_CTRL_REG(pexIf));
regVal &= ~(BIT16 | BIT19);
MV_REG_WRITE(PEX_DBG_CTRL_REG(pexIf), regVal);
}
return MV_OK;
}
/*******************************************************************************
* mvAudioHalInit - Initialize the Audio subsystem
*
* DESCRIPTION:
*
* INPUT:
* None
* OUTPUT:
* None
* RETURN:
* None
*
*******************************************************************************/
MV_VOID mvAudioHalInit(MV_U8 unit, MV_AUDIO_HAL_DATA *halData)
{
int timeout;
MV_REG_BIT_RESET(MV_AUDIO_PLL_CTRL1_REG(unit),0x333FF8);
MV_REG_BIT_SET(MV_AUDIO_PLL_CTRL1_REG(unit),0x111D18);
/*MV_REG_BIT_RESET(0x10074,0xC018000);
MV_REG_BIT_SET(0x10074,0x4008000);*/
timeout = 10000000;
while(timeout--);
MV_REG_BIT_RESET(MV_AUDIO_PLL_CTRL1_REG(unit),0x333FF8);
MV_REG_BIT_SET(MV_AUDIO_PLL_CTRL1_REG(unit),0x111D18);
mvOsMemcpy(&audioHalData[unit], halData, sizeof(MV_AUDIO_HAL_DATA));
/*MV_REG_BIT_RESET(0x10074,0xC018000);
MV_REG_BIT_SET(0x10074,0x4008000);*/
}
MV_STATUS mvTdmRx(MV_U8 *tdmRxBuff)
{
MV_TDM_CH_INFO *chInfo;
MV_U8 ch, lastBuff;
MV_U8* pTdmRxBuff;
MV_TRC_REC("->%s\n",__FUNCTION__);
/* Sanity check */
if(tdmRxBuff != rxAggrBuffVirt)
{
mvOsPrintf("%s: invalid Rx buffer !!!\n", __FUNCTION__);
return MV_ERROR;
}
if(!tdmEnable)
{
mvOsPrintf("%s: Error, no active Rx channels are available\n", __FUNCTION__);
return MV_ERROR;
}
for(ch = 0; ch < MV_TDM_TOTAL_CHANNELS; ch++)
{
chInfo = tdmChInfo[ch];
lastBuff = MV_TDM_PREV_BUFFER(chInfo->rxCurrBuff, 2);
if(chInfo->rxBuffFull[lastBuff] == BUFF_IS_EMPTY)
{
mvOsPrintf("%s: Error, Rx buffer is already empty for channel %d\n", __FUNCTION__, ch);
return MV_NOT_READY;
}
chInfo->rxBuffFull[lastBuff] = BUFF_IS_EMPTY;
MV_TRC_REC("%s get Rx buffer(%d) for channel(%d)\n",__FUNCTION__, lastBuff, ch);
pTdmRxBuff = tdmRxBuff + (ch * MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor));
/* Copy data from DMA buffer to voice engine buffer */
mvOsMemcpy(pTdmRxBuff, chInfo->rxBuffVirt[lastBuff] , MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor));
}
MV_TRC_REC("<-%s\n",__FUNCTION__);
return MV_OK;
}
MV_STATUS mvTdmTx(MV_U8 *tdmTxBuff)
{
MV_TDM_CH_INFO *chInfo;
MV_U8 nextBuff, ch;
MV_U8 *pTdmTxBuff;
MV_TRC_REC("->%s\n",__FUNCTION__);
/* Sanity check */
if(tdmTxBuff != txAggrBuffVirt)
{
mvOsPrintf("%s: Error, invalid Tx buffer !!!\n", __FUNCTION__);
return MV_ERROR;
}
if(!tdmEnable)
{
mvOsPrintf("%s: Error, no active Tx channels are available\n", __FUNCTION__);
return MV_ERROR;
}
for(ch = 0; ch < MV_TDM_TOTAL_CHANNELS; ch++)
{
chInfo = tdmChInfo[ch];
nextBuff = chInfo->txCurrBuff;
MV_TRC_REC("ch%d: fill buf %d with %d bytes\n", ch, nextBuff, MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor));
if(chInfo->txBuffFull[nextBuff] == BUFF_IS_FULL)
{
mvOsPrintf("%s: Error, Tx buffer already full for channel %d\n", __FUNCTION__, ch);
return MV_NOT_READY;
}
chInfo->txBuffFull[nextBuff] = BUFF_IS_FULL;
pTdmTxBuff = tdmTxBuff + (ch * MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor));
/* Copy data from voice engine buffer to DMA buffer */
mvOsMemcpy(chInfo->txBuffVirt[nextBuff], pTdmTxBuff , MV_TDM_CH_BUFF_SIZE(pcmFormat, tdmBandMode, factor));
}
MV_TRC_REC("<-%s\n",__FUNCTION__);
return MV_OK;
}
MV_STATUS mvCntmrHalInit(MV_CNTMR_HAL_DATA *halData)
{
mvOsMemcpy(&cntmrHalData, halData, sizeof(MV_CNTMR_HAL_DATA));
return MV_OK;
}
/*******************************************************************************
* mvUsbHalInit - Initialize USB engine
*
* DESCRIPTION:
* This function initialize USB unit. It set the default address decode
* windows of the unit.
*
* INPUT:
* None.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_ERROR if setting fail.
*******************************************************************************/
MV_STATUS mvUsbHalInit(int dev, MV_BOOL isHost, MV_USB_HAL_DATA *halData)
{
MV_U32 regVal;
MV_STATUS status = MV_OK;
mvOsMemcpy(&usbHalData, halData, sizeof(MV_USB_HAL_DATA));
/* Wait 100 usec */
mvOsUDelay(100);
/* Clear Interrupt Cause and Mask registers */
MV_REG_WRITE(MV_USB_BRIDGE_INTR_CAUSE_REG(dev), 0);
MV_REG_WRITE(MV_USB_BRIDGE_INTR_MASK_REG(dev), 0);
/* Reset controller */
regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev));
MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal | MV_USB_CORE_CMD_RESET_MASK);
while (MV_REG_READ(MV_USB_CORE_CMD_REG(dev)) & MV_USB_CORE_CMD_RESET_MASK)
;
/* Clear bit 4 in USB bridge control register for enableing core byte swap */
if ((usbHalData.ctrlModel == MV64560_DEV_ID) || (usbHalData.ctrlModel == MV64660_DEV_ID)) {
MV_REG_WRITE(MV_USB_BRIDGE_CTRL_REG(dev), (MV_REG_READ(MV_USB_BRIDGE_CTRL_REG(dev))
& ~MV_USB_BRIDGE_CORE_BYTE_SWAP_MASK));
}
/* GL# USB-10 */
/* The new register 0x360 USB 2.0 IPG Metal Fix Register
* dont' exists in the following chip revisions:
* OrionN B1 (id=0x5180, rev 3)
* Orion1 B1 (id=0x5181, rev=3) and before
* Orion1-VoIP A0 (id=0x5181, rev=8)
* Orion1-NAS A1 (id=0x5182, rev=1) and before
* Orion2 B0 (id=0x5281, rev=1) and before
*/
if (((usbHalData.ctrlModel == MV_5181_DEV_ID) &&
((usbHalData.ctrlRev <= MV_5181_B1_REV) || (usbHalData.ctrlRev == MV_5181L_A0_REV))) ||
((usbHalData.ctrlModel == MV_5182_DEV_ID) &&
(usbHalData.ctrlRev <= MV_5182_A1_REV)) ||
((usbHalData.ctrlModel == MV_5180_DEV_ID) && (usbHalData.ctrlRev <= MV_5180N_B1_REV))) {
/* Do nothing */
} else if ((usbHalData.ctrlModel == MV_6510_DEV_ID) ||
(usbHalData.ctrlModel == MV_6530_DEV_ID) ||
(usbHalData.ctrlModel == MV_6550_DEV_ID) ||
(usbHalData.ctrlModel == MV_6560_DEV_ID)) {
/* Change value of new register 0x360 */
regVal = MV_REG_READ(MV_USB_BRIDGE_IPG_REG(dev));
/* Change bits[14:8] - IPG for non Start of Frame Packets
* from 0x9(default) to 0xD
*/
regVal &= ~(0x7F << 8);
regVal |= (0xD << 8);
MV_REG_WRITE(MV_USB_BRIDGE_IPG_REG(dev), regVal);
} else {
/* Change value of new register 0x360 */
regVal = MV_REG_READ(MV_USB_BRIDGE_IPG_REG(dev));
/* Change bits[14:8] - IPG for non Start of Frame Packets
* from 0x9(default) to 0xD
*/
regVal &= ~(0x7F << 8);
regVal |= (0xD << 8);
MV_REG_WRITE(MV_USB_BRIDGE_IPG_REG(dev), regVal);
}
#ifndef MV_USB_PHY_DONT_OVERRIDE
/********* Update USB PHY configuration **********/
if ((usbHalData.ctrlModel == MV_78100_DEV_ID) ||
(usbHalData.ctrlModel == MV_78200_DEV_ID) ||
(usbHalData.ctrlModel == MV_76100_DEV_ID) ||
(usbHalData.ctrlModel == MV_6281_DEV_ID) ||
(usbHalData.ctrlModel == MV_6282_DEV_ID) ||
(usbHalData.ctrlModel == MV_6280_DEV_ID) ||
(usbHalData.ctrlModel == MV_6192_DEV_ID) ||
(usbHalData.ctrlModel == MV_6190_DEV_ID) ||
(usbHalData.ctrlModel == MV_6180_DEV_ID) ||
(usbHalData.ctrlModel == MV_6321_DEV_ID) ||
(usbHalData.ctrlModel == MV_6322_DEV_ID) ||
(usbHalData.ctrlModel == MV_6323_DEV_ID)) {
mvUsbPhy65nmNewInit(dev);
} else if ((usbHalData.ctrlModel == MV_78XX0_DEV_ID)) {
mvUsbPhy65nmInit(dev);
} else if (usbHalData.ctrlModel == MV_6183_DEV_ID) {
mvUsbPhy90nmInit(dev);
} else if ((usbHalData.ctrlModel == MV_6510_DEV_ID) ||
(usbHalData.ctrlModel == MV_6530_DEV_ID) ||
(usbHalData.ctrlModel == MV_6550_DEV_ID) ||
(usbHalData.ctrlModel == MV_6560_DEV_ID)) {
mvUsbPhy65nmNewInit(dev);
/* mvUsbPhyKW6500Init(dev); */
} else if ((usbHalData.ctrlFamily==MV_67XX) ||
(usbHalData.ctrlFamily==MV_78XX0)) {
if (mvUsbPhy40nmInit(dev))
status = MV_NOT_READY;
} else
mvUsbPhyInit(dev);
#endif
/* Set Mode register (Stop and Reset USB Core before) */
/* Stop the controller */
regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev));
regVal &= ~MV_USB_CORE_CMD_RUN_MASK;
MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal);
/* Reset the controller to get default values */
regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev));
regVal |= MV_USB_CORE_CMD_RESET_MASK;
MV_REG_WRITE(MV_USB_CORE_CMD_REG(dev), regVal);
/* Wait for the controller reset to complete */
do {
regVal = MV_REG_READ(MV_USB_CORE_CMD_REG(dev));
} while (regVal & MV_USB_CORE_CMD_RESET_MASK);
/* Set USB_MODE register */
if (isHost)
regVal = MV_USB_CORE_MODE_HOST;
else
regVal = MV_USB_CORE_MODE_DEVICE | MV_USB_CORE_SETUP_LOCK_DISABLE_MASK;
#if (MV_USB_VERSION == 0)
regVal |= MV_USB_CORE_STREAM_DISABLE_MASK;
#endif
MV_REG_WRITE(MV_USB_CORE_MODE_REG(dev), regVal);
return status;
}
MV_STATUS mvNfpFibRuleArpAdd(int family, NFP_RULE_FIB *fib2)
{
int i;
NFP_RULE_FIB *fib;
MV_STATUS status = MV_NOT_FOUND;
if (!fib_hash)
return MV_FAIL;
for (i = 0; i < NFP_FIB_HASH_SIZE; i++) {
fib = fib_hash[i];
while (fib) {
if ((l3_addr_eq(family, fib->defGtwL3, fib2->defGtwL3))) {
/* Found routing entry */
if (fib->flags & NFP_F_INV) {
if (fib2->flags & NFP_F_BRIDGE) {
#ifdef NFP_BRIDGE
NFP_RULE_BRIDGE *bridge;
/* lookup bridge database */
bridge = mvNfpBridgeLookup(fib2->bridgeOut, fib2->da);
if (bridge) {
fib->flags &= ~NFP_F_INV;
/* copy DA and SA from fib2 */
mvOsMemcpy((MV_U8 *)&fib->da, (MV_U8 *)&fib2->da, MV_MAC_ADDR_SIZE);
mvOsMemcpy((MV_U8 *)&fib->sa, (MV_U8 *)&fib2->sa, MV_MAC_ADDR_SIZE);
/* copy MH + outport + outdev from bridge */
fib->mh = bridge->mh_out;
fib->outport = bridge->outport;
fib->outdev = bridge->outdev;
}
#endif /* NFP_BRIDGE */
} else {
fib->flags &= ~NFP_F_INV;
/* copy MH (2 bytes) + DA (6 bytes) + SA (6 bytes) */
mvOsMemcpy((MV_U8 *)&fib->mh, (MV_U8 *)&fib2->mh, 2 + MV_MAC_ADDR_SIZE + MV_MAC_ADDR_SIZE);
fib->outport = fib2->outport;
fib->outdev = fib2->outdev;
}
#ifdef NFP_PNC
if ((fib->flags & NFP_F_INV) == 0)
mvNfpPncFibAdd(fib);
#endif
} else if (memcmp(fib->da, fib2->da, MV_MAC_ADDR_SIZE)) {
/* Update already valid route with new MAC address. FIXME - update HWF rule */
mvOsMemcpy(fib->da, fib2->da, MV_MAC_ADDR_SIZE);
} else {
/* Do nothing - MAC address don't changed */
}
status = MV_OK;
}
fib = fib->next;
}
}
return status;
}
/*******************************************************************************
* mvEthPhyHalInit -
*
* DESCRIPTION:
* Initialize the ethernet phy unit HAL.
*
* INPUT:
* halData - Ethernet PHY HAL data.
*
* OUTPUT:
* None.
*
* RETURN:
* MV_OK on success, MV_ERROR otherwise.
*
*******************************************************************************/
MV_STATUS mvEthPhyHalInit(MV_ETHPHY_HAL_DATA *halData)
{
mvOsMemcpy(ðphyHalData, halData, sizeof(MV_ETHPHY_HAL_DATA));
return MV_OK;
}
MV_STATUS mvPexInit(MV_U32 pexIf, MV_PEX_TYPE pexType, MV_PEX_HAL_DATA *halData)
{
MV_PEX_MODE pexMode;
MV_U32 regVal;
MV_U32 status;
MV_U16 ctrlModel, phyRegVal;
mvOsMemcpy(&pexHalData[pexIf], halData, sizeof(MV_PEX_HAL_DATA));
/* First implement Guideline (GL# PCI Express-2) Wrong Default Value */
/* to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 */
/* and 88F5281-B0 and above, 88F5182, 88F5082, 88F5181L, 88F6082/L */
ctrlModel = pexHalData[pexIf].ctrlModel;
if ((ctrlModel != MV_1281_DEV_ID) &&
(ctrlModel != MV_6281_DEV_ID) &&
(ctrlModel != MV_6282_DEV_ID) &&
(ctrlModel != MV_6280_DEV_ID) &&
(ctrlModel != MV_6192_DEV_ID) &&
(ctrlModel != MV_6190_DEV_ID) &&
(ctrlModel != MV_6180_DEV_ID) &&
(ctrlModel != MV_6183_DEV_ID) &&
(ctrlModel != MV_6183L_DEV_ID) &&
(ctrlModel != MV_78100_DEV_ID) &&
(ctrlModel != MV_78200_DEV_ID) &&
(ctrlModel != MV_76100_DEV_ID) &&
(ctrlModel != MV_6323_DEV_ID) &&
(ctrlModel != MV_6322_DEV_ID) &&
(ctrlModel != MV_6321_DEV_ID) &&
(ctrlModel != MV_78XX0_DEV_ID) &&
(ctrlModel != MV_6510_DEV_ID) &&
(ctrlModel != MV_6530_DEV_ID) && (ctrlModel != MV_6550_DEV_ID) && (ctrlModel != MV_6560_DEV_ID)) {
/* Read current value of TXAMP */
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), 0x80820000); /* Write the read command */
regVal = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); /* Extract the data */
/* Prepare new data for write */
regVal &= ~0x7; /* Clear bits [2:0] */
regVal |= 0x4; /* Set the new value */
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regVal); /* Write the write command */
} else {
/* Implement 1.0V termination GL for 88F1281 device only */
/* BIT0 - Common mode feedback */
/* BIT3 - TxBuf, extra drive for 1.0V termination */
if (ctrlModel == MV_1281_DEV_ID) {
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), 0x80860000); /* Write the read command */
regVal = MV_REG_READ(0x41b00); /* Extract the data */
regVal |= (BIT0 | BIT3);
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regVal); /* Write the write command */
MV_REG_WRITE(0x31b00, 0x80860000); /* Write the read command */
regVal = MV_REG_READ(0x31b00); /* Extract the data */
regVal |= (BIT0 | BIT3);
regVal &= ~0x80000000; /* Set "write" command */
MV_REG_WRITE(0x31b00, regVal); /* Write the write command */
}
}
if ((ctrlModel == MV_6281_DEV_ID) ||
(ctrlModel == MV_6282_DEV_ID) ||
(ctrlModel == MV_6280_DEV_ID) ||
(ctrlModel == MV_6192_DEV_ID) || (ctrlModel == MV_6190_DEV_ID) || (ctrlModel == MV_6180_DEV_ID)) {
regVal = MV_REG_READ(0x100e4); /* This register currently doesn't appear in the FS */
regVal |= 0x3 << 25;
MV_REG_WRITE(0x100e4, regVal);
}
if (ctrlModel == MV_6282_DEV_ID) {
mvPexPhyRegRead(pexIf, 0x92, &phyRegVal);
phyRegVal &= ~(0x80F0);
phyRegVal |= 0x8080;
mvPexPhyRegWrite(pexIf, 0x92, phyRegVal);
} else if ((ctrlModel == MV_6510_DEV_ID) ||
(ctrlModel == MV_6530_DEV_ID) || (ctrlModel == MV_6550_DEV_ID) || (ctrlModel == MV_6560_DEV_ID)) {
mvPexPhyRegRead(pexIf, 0x92, &phyRegVal);
phyRegVal &= ~(0x80F0);
phyRegVal |= 0x8080;
mvPexPhyRegWrite(pexIf, 0x92, phyRegVal);
}
if (mvPexModeGet(pexIf, &pexMode) != MV_OK) {
mvOsPrintf("PEX init ERR. mvPexModeGet failed (pexType=%d)\n", pexMode.pexType);
return MV_ERROR;
}
/* Check that required PEX type is the one set in reset time */
if (pexType != pexMode.pexType) {
/* No Link. Shut down the Phy */
mvPexPhyPowerDown(pexIf);
mvOsPrintf("PEX init ERR. PEX type sampled mismatch (%d,%d)\n", pexType, pexMode.pexType);
return MV_ERROR;
}
if (MV_PEX_ROOT_COMPLEX == pexType) {
mvPexLocalBusNumSet(pexIf, PEX_HOST_BUS_NUM(pexIf));
mvPexLocalDevNumSet(pexIf, PEX_HOST_DEV_NUM(pexIf));
/* Local device master Enable */
mvPexMasterEnable(pexIf, MV_TRUE);
/* Local device slave Enable */
mvPexSlaveEnable(pexIf, mvPexLocalBusNumGet(pexIf), mvPexLocalDevNumGet(pexIf), MV_TRUE);
/* Interrupt disable */
status = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND));
status |= PXSAC_INT_DIS;
MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), status);
}
mvSysPexCpuIfEnable(pexIf);
/* now wait 500 ms to be sure the link is valid (spec compliant) */
mvOsDelay(500);
/* Check if we have link */
if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) {
mvOsPrintf("PEX%d interface detected no Link.\n", pexIf);
return MV_NO_SUCH;
}
if (MV_PEX_WITDH_X1 == pexMode.pexWidth)
mvOsPrintf("PEX%d interface detected Link X1\n", pexIf);
else
mvOsPrintf("PEX%d interface detected Link X4\n", pexIf);
#ifdef PCIE_VIRTUAL_BRIDGE_SUPPORT
mvPexVrtBrgInit(pexIf);
#endif
return MV_OK;
}
MV_STATUS mvSata3HalInit(MV_SATA3_HAL_DATA *halData)
{
mvOsMemcpy(&sata3HalData, halData, sizeof(MV_SATA3_HAL_DATA));
return MV_OK;
}
