static int mx6q_seco_q7_fec_phy_reset(struct phy_device *phydev) {
int ret;
if(cpu_is_mx6q())
mxc_iomux_v3_setup_pad(MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24);
if(cpu_is_mx6dl())
mxc_iomux_v3_setup_pad(MX6DL_PAD_RGMII_RX_CTL__GPIO_6_24);
ret = gpio_request(MX6_ENET_125MHz_EN, "125mHz_en");
if (!ret) {
gpio_direction_output(MX6_ENET_125MHz_EN, 1);
gpio_set_value(MX6_ENET_125MHz_EN, 1);
printk("Resetting ethernet physical layer.\n");
gpio_set_value(MX6_SECO_Q7_FEC_RESET, 0);
msleep(2);
gpio_set_value(MX6_SECO_Q7_FEC_RESET, 1);
msleep(1);
gpio_free(MX6_ENET_125MHz_EN);
if(cpu_is_mx6q())
mxc_iomux_v3_setup_pad(MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL);
if(cpu_is_mx6dl())
mxc_iomux_v3_setup_pad(MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL);
} else {
printk(KERN_ERR "Reset of ethernet physical layer failed.\n");
}
return 0;
}
/*
* USB Host1 HS port
*/
static int gpio_usbh1_active(void)
{
iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D17__GPIO2_1;
int ret;
/* Set USBH1_STP to GPIO and toggle it */
mxc_iomux_v3_setup_pad(usbh1stp_gpio);
ret = gpio_request(MX5X_USBH1_STP, "usbh1_stp");
if (ret) {
pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
return ret;
}
gpio_direction_output(MX5X_USBH1_STP, 0);
gpio_set_value(MX5X_USBH1_STP, 1);
/* Signal only used on MX51-3DS for reset to PHY.*/
if (machine_is_mx51_3ds()) {
mxc_iomux_v3_setup_pad(phyreset_gpio);
ret = gpio_request(MX51_3DS_PHY_RESET, "eim_d17");
if (ret) {
pr_debug("failed to get MX51_PAD_EIM_D17__GPIO2_1: %d\n", ret);
return ret;
}
gpio_direction_output(MX51_3DS_PHY_RESET, 0);
gpio_set_value(MX51_3DS_PHY_RESET, 1);
}
msleep(100);
return 0;
}
void spi_io_init(struct imx_spi_dev_t *dev)
{
u32 reg;
switch (dev->base) {
case ECSPI1_BASE_ADDR:
/* Enable clock */
reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR1);
reg |= 0x3;
writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR1);
/* SCLK */
mxc_iomux_v3_setup_pad(MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK);
/* MISO */
mxc_iomux_v3_setup_pad(MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO);
/* MOSI */
mxc_iomux_v3_setup_pad(MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI);
if (dev->ss == 0)
mxc_iomux_v3_setup_pad
(MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0);
break;
case ECSPI2_BASE_ADDR:
case ECSPI3_BASE_ADDR:
/* ecspi2-3 fall through */
break;
default:
break;
}
}
static void setup_epdc_power(void)
{
unsigned int reg;
/* Setup epdc voltage */
/* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */
mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13);
/* EPDC_VCOM0 - GPIO2[3] for VCOM control */
mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_VCOM0__GPIO_2_3);
/* Set as output */
reg = readl(GPIO2_BASE_ADDR + GPIO_GDIR);
reg |= (1 << 3);
writel(reg, GPIO2_BASE_ADDR + GPIO_GDIR);
/* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */
mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14);
/* Set as output */
reg = readl(GPIO2_BASE_ADDR + GPIO_GDIR);
reg |= (1 << 14);
writel(reg, GPIO2_BASE_ADDR + GPIO_GDIR);
/* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */
mxc_iomux_v3_setup_pad(MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7);
/* Set as output */
reg = readl(GPIO2_BASE_ADDR + GPIO_GDIR);
reg |= (1 << 7);
writel(reg, GPIO2_BASE_ADDR + GPIO_GDIR);
}
/* set 1 to output, sent 0 to input */
static void mx6sl_i2c_gpio_sda_direction(int bus, int output)
{
u32 reg;
switch (bus) {
case 1:
mxc_iomux_v3_setup_pad(MX6SL_PAD_I2C1_SDA__GPIO_3_13);
reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
if (output)
reg |= I2C1_SDA_GPIO3_13_BIT_MASK;
else
reg &= ~I2C1_SDA_GPIO3_13_BIT_MASK;
writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
break;
case 2:
mxc_iomux_v3_setup_pad(MX6SL_PAD_I2C2_SDA__GPIO_3_15);
reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR);
if (output)
reg |= I2C2_SDA_GPIO3_15_BIT_MASK;
else
reg &= ~I2C2_SDA_GPIO3_15_BIT_MASK;
writel(reg, GPIO3_BASE_ADDR + GPIO_GDIR);
break;
}
}
static void setup_i2c(unsigned int module_base)
{
unsigned int reg;
switch (module_base) {
case I2C1_BASE_ADDR:
/* i2c1 SDA */
mxc_iomux_v3_setup_pad(MX6SL_PAD_I2C1_SDA__I2C1_SDA);
/* i2c1 SCL */
mxc_iomux_v3_setup_pad(MX6SL_PAD_I2C1_SCL__I2C1_SCL);
/* Enable i2c clock */
reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
reg |= 0xC0;
writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
break;
case I2C2_BASE_ADDR:
/* i2c2 SDA */
mxc_iomux_v3_setup_pad(MX6SL_PAD_I2C2_SDA__I2C2_SDA);
/* i2c2 SCL */
mxc_iomux_v3_setup_pad(MX6SL_PAD_I2C2_SCL__I2C2_SCL);
/* Enable i2c clock */
reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2);
reg |= 0x300;
writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR2);
break;
default:
printf("Invalid I2C base: 0x%x\n", module_base);
break;
}
}
static int gpio_usbh1_active(void)
{
iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
int ret;
/* Set USBH1_STP to GPIO and toggle it */
mxc_iomux_v3_setup_pad(usbh1stp_gpio);
ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
if (ret) {
pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
return ret;
}
gpio_direction_output(BABBAGE_USBH1_STP, 0);
gpio_set_value(BABBAGE_USBH1_STP, 1);
msleep(100);
gpio_free(BABBAGE_USBH1_STP);
/* De-assert USB PHY RESETB */
mxc_iomux_v3_setup_pad(phyreset_gpio);
ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
if (ret) {
pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
return ret;
}
gpio_direction_output(BABBAGE_PHY_RESET, 1);
return 0;
}
static int initialize_usbh1_port(struct platform_device *pdev)
{
iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
u32 v;
void __iomem *usb_base;
void __iomem *socregs_base;
mxc_iomux_v3_setup_pad(usbh1gpio);
gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
gpio_direction_output(EFIKAMX_USBH1_STP, 0);
msleep(1);
gpio_set_value(EFIKAMX_USBH1_STP, 1);
msleep(1);
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
/* The clock for the USBH1 ULPI port will come externally */
/* from the PHY. */
v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
socregs_base + MX51_USB_CTRL_1_OFFSET);
iounmap(usb_base);
gpio_free(EFIKAMX_USBH1_STP);
mxc_iomux_v3_setup_pad(usbh1stp);
mdelay(10);
return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD);
}
static void ov5640_mipi_camera_io_init(void)
{
struct clk *clko1;
if (cpu_is_mx6q())
{
mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_MCLK__CCM_CLKO);
mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT18__GPIO_6_4);
}
else
{
mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_MCLK__CCM_CLKO);
mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT18__GPIO_6_4);
}
clko1 = clk_get(NULL, "clko_clk");
if (IS_ERR(clko1)) {
pr_err("can't get CLKO1 clock.\n");
} else {
long round = clk_round_rate(clko1, 27000000);
clk_set_rate(clko1, round);
clk_enable(clko1);
}
/* Camera reset */
gpio_request(MX6_CAMERA_RST, "cam-reset");
gpio_direction_output(MX6_CAMERA_RST, 0);
msleep(1);
gpio_set_value(MX6_CAMERA_RST, 1);
msleep(100);
/* for mx6dl, mipi virtual channel 1 connect to csi 0*/
if (cpu_is_mx6dl())
mxc_iomux_set_gpr_register(13, 0, 3, 0);
}
/* workaround for ecspi chipselect pin may not keep correct level when idle */
static void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status,
int chipselect)
{
switch (cspi_mode) {
case 1:
switch (chipselect) {
case 0x1:
{
iomux_v3_cfg_t cspi1_ss0 = MX51_PAD_CSPI1_SS0__ECSPI1_SS0;
mxc_iomux_v3_setup_pad(cspi1_ss0);
break;
}
case 0x2:
{
iomux_v3_cfg_t cspi1_ss0_gpio = MX51_PAD_CSPI1_SS0__GPIO4_24;
mxc_iomux_v3_setup_pad(cspi1_ss0_gpio);
gpio_request(BABBAGE_CSP1_SS0_GPIO, "cspi1-gpio");
gpio_direction_output(BABBAGE_CSP1_SS0_GPIO, 0);
gpio_set_value(BABBAGE_CSP1_SS0_GPIO, 1 & (~status));
break;
}
default:
break;
}
break;
case 2:
break;
case 3:
break;
default:
break;
}
}
static void __init imx6q_seco_q7_init_usb(void) {
int ret = 0;
imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
/* disable external charger detect,
* or it will affect signal quality at dp .
*/
ret = gpio_request(MX6_SECO_A62_USB_OTG_PWR, "usb-pwr");
if (ret) {
pr_err("failed to get GPIO MX6_SECO_A62_USB_OTG_PWR: %d\n",
ret);
return;
}
gpio_direction_output(MX6_SECO_A62_USB_OTG_PWR, 0);
mxc_iomux_set_gpr_register(1, 13, 1, 0);
/*
* Setting pad control for OTG ID pin UP because the OTG port
* is used only as client
*/
if (cpu_is_mx6q())
mxc_iomux_v3_setup_pad(mx6qd_seco_a62_otg_id_up_pads);
else if (cpu_is_mx6dl())
mxc_iomux_v3_setup_pad(mx6sdl_seco_a62_otg_id_up_pads);
mx6_set_otghost_vbus_func(imx6q_seco_q7_usbotg_vbus);
// mx6_usb_dr_init();
// mx6_usb_h1_init();
}
static void setup_uart(void)
{
/* UART1 TXD */
mxc_iomux_v3_setup_pad(MX6SL_PAD_UART1_TXD__UART1_TXD);
/* UART1 RXD */
mxc_iomux_v3_setup_pad(MX6SL_PAD_UART1_RXD__UART1_RXD);
}
static void __init mx50_rdp_io_init(void)
{
iomux_v3_cfg_t cspi_keeper = (MX50_PAD_ECSPI1_SCLK__GPIO_4_12 & ~MUX_PAD_CTRL_MASK);
iomux_v3_cfg_t *p = mx50_rdp;
int i;
/* Set PADCTRL to 0 for all IOMUX. */
for (i = 0; i < ARRAY_SIZE(mx50_rdp); i++) {
iomux_v3_cfg_t pad_ctl = *p;
pad_ctl &= ~MUX_PAD_CTRL_MASK;
mxc_iomux_v3_setup_pad(pad_ctl);
p++;
}
mxc_iomux_v3_setup_multiple_pads(mx50_rdp, \
ARRAY_SIZE(mx50_rdp));
gpio_request(SD1_WP, "sdhc1-wp");
gpio_direction_input(SD1_WP);
gpio_request(SD1_CD, "sdhc1-cd");
gpio_direction_input(SD1_CD);
//gpio_request(WIFI_RESET, "wifi-reset");
//gpio_direction_output(WIFI_RESET,1);
gpio_request(SD_POWER, "sd-power");
gpio_direction_output(SD_POWER,0);
// Power on, clean the SD1_CHANGE_FOUND.
//printk("Clean SD changed event.\n");
gpio_request(SD1_CHANGE_CLEAR, "sd-clear");
gpio_direction_output(SD1_CHANGE_CLEAR,1);
mdelay(1);
gpio_direction_output(SD1_CHANGE_CLEAR,0);
gpio_request(SD1_CHANGE_FOUND, "sd-found");
gpio_direction_input(SD1_CHANGE_FOUND);
#ifdef CONFIG_MACH_MX50_NIMBUS_RESCUE
nimbus_led_ctrl(LEDID_CHARGER_RED,0,1);
nimbus_led_ctrl(LEDID_CHARGER_GREEN,0,0);
#endif
gpio_request(POWER_KET_DET, "power-key-detect");
gpio_direction_input(POWER_KET_DET);
gpio_request(WDOG_B, "wdog-b");
gpio_direction_input(WDOG_B);
/* USB OTG PWR */
gpio_request(USB_OTG_PWR, "usb otg power");
gpio_direction_output(USB_OTG_PWR, 0);
/* Disable all keepers */
mxc_iomux_v3_setup_pad(cspi_keeper);
}
void udc_pins_setting(void)
{
/* USB_OTG_PWR */
mxc_iomux_v3_setup_pad(MX6SL_PAD_KEY_COL4__GPIO_4_0);
mxc_iomux_v3_setup_pad(MX6SL_PAD_KEY_COL5__GPIO_4_2);
/* USB_OTG_PWR = 0 */
gpio_direction_output(USB_OTG_PWR, 0);
/* USB_H1_POWER = 1 */
gpio_direction_output(USB_H1_PWR, 1);
}
static void hsic_start(void)
{
pr_debug("%s", __func__);
/* strobe 47K pull up */
if (cpu_is_mx6q())
mxc_iomux_v3_setup_pad(
MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE_START);
else if (cpu_is_mx6dl())
mxc_iomux_v3_setup_pad(
MX6DL_PAD_RGMII_RXC__USBOH3_H3_STROBE_START);
}
/*
* Board specific initialization.
*/
static void __init mx51_babbage_init(void)
{
iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
imx51_soc_init();
#if defined(CONFIG_CPU_FREQ_IMX)
get_cpu_op = mx51_get_cpu_op;
#endif
mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
ARRAY_SIZE(mx51babbage_pads));
imx51_add_imx_uart(0, &uart_pdata);
imx51_add_imx_uart(1, NULL);
imx51_add_imx_uart(2, &uart_pdata);
babbage_fec_reset();
imx51_add_fec(NULL);
/* Set the PAD settings for the pwr key. */
mxc_iomux_v3_setup_pad(power_key);
imx_add_gpio_keys(&imx_button_data);
imx51_add_imx_i2c(0, &babbage_i2c_data);
imx51_add_imx_i2c(1, &babbage_i2c_data);
mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
if (otg_mode_host)
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
else {
initialize_otg_port(NULL);
mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
}
gpio_usbh1_active();
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
/* setback USBH1_STP to be function */
mxc_iomux_v3_setup_pad(usbh1stp);
babbage_usbhub_reset();
imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
imx51_add_imx2_wdt(0, NULL);
}
static void __init armadillo_box_ws1_bp35a1_init(void)
{
mxc_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28);
mxc_iomux_v3_setup_pad(MX25_PAD_RTCK__GPIO_3_14);
gpio_request(UART3_RTS, "UART3_RTS");
gpio_request(BP35A1_RESET, "BP35A1_RESET");
gpio_direction_output(UART3_RTS, UART3_RTS_ASSERT);
/* reset */
gpio_direction_output(BP35A1_RESET, BP35A1_RESET_ASSERT);
ndelay(500);
gpio_direction_output(BP35A1_RESET, BP35A1_RESET_DEASSERT);
}
/*
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
ARRAY_SIZE(mx51babbage_pads));
mxc_init_imx_uart();
platform_add_devices(devices, ARRAY_SIZE(devices));
mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
if (otg_mode_host)
mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
else {
initialize_otg_port(NULL);
mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
}
gpio_usbh1_active();
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
/* setback USBH1_STP to be function */
mxc_iomux_v3_setup_pad(&usbh1stp);
babbage_usbhub_reset();
imx51_add_esdhc(0, NULL);
imx51_add_esdhc(1, NULL);
}
static void nimbus_gpio_iomux_init()
{
iomux_v3_cfg_t iomux_setting;
iomux_setting = (MX50_PAD_ECSPI2_SCLK__GPIO_4_16 & \
~MUX_PAD_CTRL_MASK) | \
MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DSE_HIGH);
/* Enable the Pull/keeper */
mxc_iomux_v3_setup_pad(iomux_setting);
nimbus_led_ctrl(LEDID_WLAN,0,0);
nimbus_led_ctrl(LEDID_WIFI,0,0);
nimbus_led_ctrl(LEDID_CHARGER_RED,0,0);
nimbus_led_ctrl(LEDID_CHARGER_GREEN,0,0);
#if 0
if( gpio_get_value(SD1_CHANGE_FOUND)==0)
{
printk("Found SD changed during suspending.\n");
}
gpio_direction_output(SD1_CHANGE_CLEAR,1);
mdelay(1);
gpio_direction_output(SD1_CHANGE_CLEAR,0);
#endif
}
static void mx50_suspend_exit()
{
iomux_v3_cfg_t iomux_setting =
(MX50_PAD_ECSPI2_SCLK__GPIO_4_16 &
~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x84);
/* Power Up the band-gap and set the SELFBIAS bit. */
__raw_writel(MXC_ANADIG_REF_PWD,
apll_base + MXC_ANADIG_MISC_CLR);
udelay(100);
__raw_writel(MXC_ANADIG_REF_SELFBIAS_OFF,
apll_base + MXC_ANADIG_MISC_SET);
//if (board_is_mx50_rd3()) {
/* Enable the Pull/keeper */
mxc_iomux_v3_setup_pad(iomux_setting);
gpio_request(DCDC_EN, "dcdc-en");
gpio_direction_output(DCDC_EN, 1);
//}
mxc_iomux_v3_setup_multiple_pads(suspend_exit_pads,
ARRAY_SIZE(suspend_exit_pads));
nimbus_gpio_iomux_init();
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret = 0;
struct clk *usb_clk;
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
/* on mx53, there is a hardware limitation that when switch the host2's clk mode
* ,usb phy1 clk must be on, after finish switching this clk can be off */
if (cpu_is_mx53()) {
usb_clk = clk_get(NULL, "usb_phy1_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
}
ret = fsl_usb_host_init(pdev);
if (cpu_is_mx53()) {
usb_clk = clk_get(NULL, "usb_phy1_clk");
clk_disable(usb_clk);
clk_put(usb_clk);
}
/* setback USBH2_STP to be function */
mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__USBH2_STP);
return ret;
}
static int efikamx_usb_init(void)
{
if (!of_machine_is_compatible("genesi,imx51-sb"))
return 0;
barebox_set_hostname("efikasb");
mc13xxx_register_init_callback(efikamx_power_init);
gpio_direction_output(GPIO_BLUETOOTH, 0);
gpio_direction_output(GPIO_WIFI_ENABLE, 1);
gpio_direction_output(GPIO_WIFI_RESET, 0);
gpio_direction_output(GPIO_SMSC3317_RESET, 0);
gpio_direction_output(GPIO_HUB_RESET, 0);
gpio_direction_output(GPIO_BACKLIGHT_POWER, 1);
mdelay(10);
gpio_set_value(GPIO_HUB_RESET, 1);
gpio_set_value(GPIO_SMSC3317_RESET, 1);
gpio_set_value(GPIO_BLUETOOTH, 1);
gpio_set_value(GPIO_WIFI_RESET, 1);
mxc_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__GPIO1_27);
gpio_set_value(IMX_GPIO_NR(1, 27), 1);
mdelay(1);
mxc_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
if (machine_is_efikasb()) {
mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__GPIO2_20);
gpio_set_value(IMX_GPIO_NR(2, 20), 1);
mdelay(1);
mxc_iomux_v3_setup_pad(MX51_PAD_EIM_A26__USBH2_STP);
}
switch (bootsource_get()) {
case BOOTSOURCE_MMC:
of_device_enable_path("/chosen/environment-sd");
break;
case BOOTSOURCE_SPI:
default:
of_device_enable_path("/chosen/environment-spi");
break;
}
return 0;
}
static void disable_pwm2_pad(void)
{
mxc_iomux_v3_setup_pad(mx53_ard_pwm_pads[3]);
gpio_request(ARD_PWM2_OFF, "pwm2-off");
gpio_direction_output(ARD_PWM2_OFF, 1);
gpio_free(ARD_PWM2_OFF);
}
static void __init armadillo4x0_rtc_init(void)
{
mxc_iomux_v3_setup_pad(MX25_PAD_RTCK__GPIO_3_14);
gpio_request(RTC_ALM_INT, "RTC_ALM_INT");
gpio_direction_input(RTC_ALM_INT);
armadillo4x0_i2c1[0].irq = gpio_to_irq(RTC_ALM_INT);
}
/* workaround for cspi chipselect pin may not keep correct level when idle */
static void mx50_rdp_gpio_spi_chipselect_active(int cspi_mode, int status,
int chipselect)
{
switch (cspi_mode) {
case 1:
break;
case 2:
break;
case 3:
switch (chipselect) {
case 0x1:
{
iomux_v3_cfg_t cspi_ss0 = MX50_PAD_CSPI_SS0__CSPI_SS0;
iomux_v3_cfg_t cspi_cs1 = MX50_PAD_ECSPI1_MOSI__GPIO_4_13;
/* pull up/down deassert it */
mxc_iomux_v3_setup_pad(cspi_ss0);
mxc_iomux_v3_setup_pad(cspi_cs1);
gpio_request(CSPI_CS1, "cspi-cs1");
gpio_direction_input(CSPI_CS1);
}
break;
case 0x2:
{
iomux_v3_cfg_t cspi_ss1 = MX50_PAD_ECSPI1_MOSI__CSPI_SS1;
iomux_v3_cfg_t cspi_ss0 = MX50_PAD_CSPI_SS0__GPIO_4_11;
/*disable other ss */
mxc_iomux_v3_setup_pad(cspi_ss1);
mxc_iomux_v3_setup_pad(cspi_ss0);
/* pull up/down deassert it */
gpio_request(CSPI_CS2, "cspi-cs2");
gpio_direction_input(CSPI_CS2);
}
break;
default:
break;
}
break;
default:
break;
}
}
static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
{
struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
int ret;
ret = gpio_request(AC97_GPIO_TXFS, "SSI");
if (ret)
goto err1;
ret = gpio_request(AC97_GPIO_TXD, "SSI");
if (ret)
goto err2;
ret = gpio_request(AC97_GPIO_RESET, "SSI");
if (ret)
goto err3;
mxc_iomux_v3_setup_pad(&txfs_gpio);
mxc_iomux_v3_setup_pad(&txd_gpio);
mxc_iomux_v3_setup_pad(&reset_gpio);
gpio_direction_output(AC97_GPIO_TXFS, 0);
gpio_direction_output(AC97_GPIO_TXD, 0);
/* cold reset */
gpio_direction_output(AC97_GPIO_RESET, 0);
udelay(10);
gpio_direction_output(AC97_GPIO_RESET, 1);
mxc_iomux_v3_setup_pad(&txd);
mxc_iomux_v3_setup_pad(&txfs);
gpio_free(AC97_GPIO_RESET);
err3:
gpio_free(AC97_GPIO_TXD);
err2:
gpio_free(AC97_GPIO_TXFS);
err1:
if (ret)
printk("%s failed with %d\n", __func__, ret);
mdelay(1);
}
static int initialize_usbh2_port(struct platform_device *pdev)
{
iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
mxc_iomux_v3_setup_pad(usbh2gpio);
gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
gpio_direction_output(EFIKASB_USBH2_STP, 0);
msleep(1);
gpio_set_value(EFIKASB_USBH2_STP, 1);
msleep(1);
gpio_free(EFIKASB_USBH2_STP);
mxc_iomux_v3_setup_pad(usbh2stp);
mdelay(10);
return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
}
static void __init mx50_arm2_io_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx50_armadillo2, \
ARRAY_SIZE(mx50_armadillo2));
gpio_request(SD1_WP, "sdhc1-wp");
gpio_direction_input(SD1_WP);
gpio_request(SD1_CD, "sdhc1-cd");
gpio_direction_input(SD1_CD);
gpio_request(SD2_WP, "sdhc2-wp");
gpio_direction_input(SD2_WP);
gpio_request(SD2_CD, "sdhc2-cd");
gpio_direction_input(SD2_CD);
gpio_request(SD3_WP, "sdhc3-wp");
gpio_direction_input(SD3_WP);
gpio_request(SD3_CD, "sdhc3-cd");
gpio_direction_input(SD3_CD);
gpio_request(HP_DETECT, "hp-det");
gpio_direction_input(HP_DETECT);
gpio_request(PWR_INT, "pwr-int");
gpio_direction_input(PWR_INT);
gpio_request(EPDC_PMIC_WAKE, "epdc-pmic-wake");
gpio_direction_output(EPDC_PMIC_WAKE, 0);
gpio_request(EPDC_VCOM, "epdc-vcom");
gpio_direction_output(EPDC_VCOM, 0);
gpio_request(EPDC_PMIC_INT, "epdc-pmic-int");
gpio_direction_input(EPDC_PMIC_INT);
gpio_request(EPDC_PWRSTAT, "epdc-pwrstat");
gpio_direction_input(EPDC_PWRSTAT);
/* ELCDIF backlight */
gpio_request(EPDC_ELCDIF_BACKLIGHT, "elcdif-backlight");
gpio_direction_output(EPDC_ELCDIF_BACKLIGHT, 1);
if (enable_w1) {
iomux_v3_cfg_t one_wire = MX50_PAD_OWIRE__OWIRE;
mxc_iomux_v3_setup_pad(one_wire);
}
/* USB OTG PWR */
gpio_request(USB_OTG_PWR, "usb otg power");
gpio_direction_output(USB_OTG_PWR, 1);
gpio_set_value(USB_OTG_PWR, 0);
}
static void ti_wifi_init(void)
{
// Make sure your GPIO & PAD setting is match
mxc_iomux_v3_setup_pad(MX50_PAD_KEY_ROW0__GPIO_4_1);
gpio_request(WLAN_IRQ_IO, "wlan_irq");
gpio_direction_input(WLAN_IRQ_IO);
mxc_iomux_v3_setup_pad(MX50_PAD_KEY_ROW1__GPIO_4_3);
gpio_request(WLAN_EN_IO, "wlan_en");
#ifdef CONFIG_MACH_MX50_NIMBUS_TI_WIFI_PM_PATCH
gpio_direction_output(WLAN_EN_IO , 0);
#else
gpio_direction_output(WLAN_EN_IO , 1);
#endif
if (wl12xx_set_platform_data(&ti_wlan_data))
{
pr_err("Error setting wl12xx data\n");
}
}
int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
{
struct pad_desc *p = pad_list;
int i;
for (i = 0; i < count; i++) {
mxc_iomux_v3_setup_pad(p);
p++;
}
return 0;
}
